llvm/lib/Target/Mips/Disassembler, branch testinghttp://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/Mips/Disassembler?h=testing2013-02-14T03:05:25ZRemove the form field from Mips16 instruction formats and set things2013-02-14T03:05:25ZReed Kotlerrkotler@mips.com2013-02-14T03:05:25Zurn:sha1:38f85c5b9f2e2a7e1364ce44b6b8cd1ec0ffb0b3
up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what is already
there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8
This is a resubmittal. For some reason it broke the bots yesterday2013-01-19T02:00:40ZJack Carterjcarter@mips.com2013-01-19T02:00:40Zurn:sha1:e11dda8631f1e65417971ee0c2f7a661fc7d0fd7
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Formatting fixes. Mostly long lines and
blank spaces at end of lines.
Contributer: Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172882 91177308-0d34-0410-b5e6-96231b3b80d8
This is a resubmittal. For some reason it broke the bots yesterday2013-01-17T00:28:20ZJack Carterjcarter@mips.com2013-01-17T00:28:20Zurn:sha1:c147b678206db510336ee95c3b55dc9c0ff19595
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
reverting 1725792013-01-16T01:29:10ZJack Carterjcarter@mips.com2013-01-16T01:29:10Zurn:sha1:457ee1a12e2c52624af7fdb81cf938f6d8d96572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
Akira,2013-01-16T00:07:45ZJack Carterjcarter@mips.com2013-01-16T00:07:45Zurn:sha1:490c7d97737ea7719efcea7321d3cfa3984b0027
Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a warning. [-Wunused-function]2013-01-12T15:37:00ZNAKAMURA Takumigeek4civic@gmail.com2013-01-12T15:37:00Zurn:sha1:edaf85606d7ac8368dd7fa0e9fd4042e523a6e3a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172319 91177308-0d34-0410-b5e6-96231b3b80d8
Remove edis - the enhanced disassembler. Fixes PR14654.2012-12-19T19:55:47ZRoman Divackyrdivacky@freebsd.org2012-12-19T19:55:47Zurn:sha1:759e3fa641d0ad01012d16d913015c9f69c8d2ab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
Use the new script to sort the includes of every file under lib.2012-12-03T16:50:05ZChandler Carruthchandlerc@gmail.com2012-12-03T16:50:05Zurn:sha1:d04a8d4b33ff316ca4cf961e06c9e312eff8e64f
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
MIPS DSP: add functions which decode DSP and accumulator registers.2012-09-27T02:01:10ZAkira Hatanakaahatanaka@mips.com2012-09-27T02:01:10Zurn:sha1:5e69cef21bad39f796f8b2bee4117c04a10b0238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164748 91177308-0d34-0410-b5e6-96231b3b80d8
Switch the fixed-length disassembler to be table-driven.2012-08-14T19:06:05ZJim Grosbachgrosbach@apple.com2012-08-14T19:06:05Zurn:sha1:fc1a161d76f5cc0204bed3bce3e27cf36ac76d22
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.
As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:
Time to compile at -O2 (averaged w/ hot caches):
Previous: 35.5s
New: 8.9s
TEXT size:
Previous: 447,251
New: 297,661
Builds in 25% of the time previously required and generates code 66% of
the size.
Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8