llvm/lib/Target/Mips/Disassembler, branch release_32http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/Mips/Disassembler?h=release_322012-09-27T02:01:10ZMIPS DSP: add functions which decode DSP and accumulator registers.2012-09-27T02:01:10ZAkira Hatanakaahatanaka@mips.com2012-09-27T02:01:10Zurn:sha1:5e69cef21bad39f796f8b2bee4117c04a10b0238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164748 91177308-0d34-0410-b5e6-96231b3b80d8
Switch the fixed-length disassembler to be table-driven.2012-08-14T19:06:05ZJim Grosbachgrosbach@apple.com2012-08-14T19:06:05Zurn:sha1:fc1a161d76f5cc0204bed3bce3e27cf36ac76d22
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.
As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:
Time to compile at -O2 (averaged w/ hot caches):
Previous: 35.5s
New: 8.9s
TEXT size:
Previous: 447,251
New: 297,661
Builds in 25% of the time previously required and generates code 66% of
the size.
Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply r158846.2012-07-09T18:46:47ZAkira Hatanakaahatanaka@mips.com2012-07-09T18:46:47Zurn:sha1:241b77fa451f8076e47c37212028454ad52ece15
Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
revert r159851.2012-07-06T20:16:48ZAkira Hatanakaahatanaka@mips.com2012-07-06T20:16:48Zurn:sha1:63d10fbc89c02758cd91e3b53749e55c2bd0cf65
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply r158846.2012-07-06T19:29:11ZAkira Hatanakaahatanaka@mips.com2012-07-06T19:29:11Zurn:sha1:e32cc0d5456eb7beb4030f0c0205c724a485ff31
Include file MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r158846.2012-06-20T21:19:39ZAkira Hatanakaahatanaka@mips.com2012-06-20T21:19:39Zurn:sha1:02a227af91889d39f5e811e2e27ecce8144499eb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
In MipsDisassembler.cpp, instead of defining register class tables, use the ones2012-06-20T20:39:23ZAkira Hatanakaahatanaka@mips.com2012-06-20T20:39:23Zurn:sha1:b66510f309077d9f616462a1696f712236ce5a22
that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.
Also, fix bug in function DecodeAFGR64RegisterClass.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
Use uint16_t to store registers in static tables. Matches other tables.2012-05-24T06:09:56ZCraig Toppercraig.topper@gmail.com2012-05-24T06:09:56Zurn:sha1:c5ce4d1d52a30c52c2ffa8d281e874db4d7f3eda
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157375 91177308-0d34-0410-b5e6-96231b3b80d8
Move MipsDisassembler classes into an anonymous namespace.2012-05-01T14:34:24ZBenjamin Kramerbenny.kra@googlemail.com2012-05-01T14:34:24Zurn:sha1:0998627b24a1f183920e782abf717e25cbb1a5f5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155915 91177308-0d34-0410-b5e6-96231b3b80d8
Delete latter half of CMakeLists.txt.2012-04-17T18:18:09ZAkira Hatanakaahatanaka@mips.com2012-04-17T18:18:09Zurn:sha1:b90757078f6c270f0b4138dde10a02bd3b64750f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154936 91177308-0d34-0410-b5e6-96231b3b80d8