llvm/lib/Target/Mips/AsmParser, branch stablehttp://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/Mips/AsmParser?h=stable2013-03-22T00:05:30ZThis patch that enables the Mips assembler to use symbols for offset for instructions2013-03-22T00:05:30ZJack Carterjack.carter@imgtec.com2013-03-22T00:05:30Zurn:sha1:25df6a93f3324bd30f44dcb95fd17aff0a92d438
This patch uses the generated instruction info tables to
identify memory/load store instructions.
After successful matching and based on the operand type
and size, it generates additional instructions to the output.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
This patch enables the Mips .set directive to define aliases2013-03-21T21:44:16ZJack Carterjack.carter@imgtec.com2013-03-21T21:44:16Zurn:sha1:c91b5e197bb41ccb2f9f78b6176e61c848df9e15
The .set directive in the Mips the assembler can be
used to set the value of a symbol to an expression.
This changes the symbol's value and type to conform
to the expression's.
Syntax: .set symbol, expression
This patch implements the parsing of the above syntax
and enables the parser to use defined symbols when
parsing operands.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667 91177308-0d34-0410-b5e6-96231b3b80d8
Silence anonymous type in anonymous union warnings.2013-03-15T00:42:55ZEric Christopherechristo@gmail.com2013-03-15T00:42:55Zurn:sha1:a286fc065a5bc846d73c8407a534a1d3c1d70b59
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8
Mips specific standalone assembler addressing mode %hi and %lo.2013-02-21T02:09:31ZJack Carterjcarter@mips.com2013-02-21T02:09:31Zurn:sha1:77217229ba1bbc92f3a53099fa91bcdaa7797da8
The constructs %hi() and %lo() represent the high and low 16
bits of the address.
Because the 16 bit offset field of an LW instruction is
interpreted as signed, if bit 15 of the low part is 1 then the
low part will act as a negative and 1 needs to be added to the
high part.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175707 91177308-0d34-0410-b5e6-96231b3b80d8
ELF symbol table field st_other support, 2013-02-20T23:11:17ZJack Carterjcarter@mips.com2013-02-20T23:11:17Zurn:sha1:99e98551bf8719764f9345ce856118f3f1a9c441
excluding visibility bits.
Mips specific standalone assembler directive "set at".
This directive changes the general purpose register
that the assembler will use when given the symbolic
register name $at.
This does not include negative testing. That will come
in a future patch.
A side affect of this patch recognizes the different
GPR register names for temporaries between old abi
and new abi so a test case for that is included.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175686 91177308-0d34-0410-b5e6-96231b3b80d8
MCParser: Update method names per coding guidelines.2013-02-20T22:21:35ZJim Grosbachgrosbach@apple.com2013-02-20T22:21:35Zurn:sha1:cb2ae3d98e3bb36e5813f8f69b00d39efd026dcd
s/AddDirectiveHandler/addDirectiveHandler/
s/ParseMSInlineAsm/parseMSInlineAsm/
s/ParseIdentifier/parseIdentifier/
s/ParseStringToEndOfStatement/parseStringToEndOfStatement/
s/ParseEscapedString/parseEscapedString/
s/EatToEndOfStatement/eatToEndOfStatement/
s/ParseExpression/parseExpression/
s/ParseParenExpression/parseParenExpression/
s/ParseAbsoluteExpression/parseAbsoluteExpression/
s/CheckForValidSection/checkForValidSection/
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175675 91177308-0d34-0410-b5e6-96231b3b80d8
This patch implements parsing the .word2013-01-25T01:31:34ZJack Carterjcarter@mips.com2013-01-25T01:31:34Zurn:sha1:801c5838830d190a6b0d8e462bd43805f66ba50f
directive for the Mips assembler.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173407 91177308-0d34-0410-b5e6-96231b3b80d8
This is a resubmittal. For some reason it broke the bots yesterday2013-01-17T00:28:20ZJack Carterjcarter@mips.com2013-01-17T00:28:20Zurn:sha1:c147b678206db510336ee95c3b55dc9c0ff19595
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
reverting 1725792013-01-16T01:29:10ZJack Carterjcarter@mips.com2013-01-16T01:29:10Zurn:sha1:457ee1a12e2c52624af7fdb81cf938f6d8d96572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
Akira,2013-01-16T00:07:45ZJack Carterjcarter@mips.com2013-01-16T00:07:45Zurn:sha1:490c7d97737ea7719efcea7321d3cfa3984b0027
Hope you are feeling better.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8