http://llvm.org https://git.amat.us/llvm/atom/lib/Target/MBlaze/Makefile?h=testing 2012-12-19T19:55:47Z 2012-12-19T19:55:47Z Roman Divacky rdivacky@freebsd.org 2012-12-19T19:55:47Z urn:sha1:759e3fa641d0ad01012d16d913015c9f69c8d2ab git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8 2011-07-14T20:59:42Z Evan Cheng evan.cheng@apple.com 2011-07-14T20:59:42Z urn:sha1:c60f9b752381baa6c4b80c0739034660f1748c84 registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8 2011-07-01T22:36:09Z Evan Cheng evan.cheng@apple.com 2011-07-01T22:36:09Z urn:sha1:385e930d55f3ecd3c9538823dfa5896a12461845 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8 2011-06-28T20:07:07Z Evan Cheng evan.cheng@apple.com 2011-06-28T20:07:07Z urn:sha1:22fee2dff4c43b551aefa44a96ca74fcade6bfac git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8 2011-06-27T18:32:37Z Evan Cheng evan.cheng@apple.com 2011-06-27T18:32:37Z urn:sha1:73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8 2011-06-24T01:44:41Z Evan Cheng evan.cheng@apple.com 2011-06-24T01:44:41Z urn:sha1:a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8 2010-12-09T03:42:04Z Wesley Peck peckw@wesleypeck.com 2010-12-09T03:42:04Z urn:sha1:8397be042766f1913ceaa2b3e6782de0322bbe6a git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121355 91177308-0d34-0410-b5e6-96231b3b80d8 2010-10-27T00:23:01Z Wesley Peck peckw@wesleypeck.com 2010-10-27T00:23:01Z urn:sha1:a06038369b830bb83742b6b39775f39dd9e69ae2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117420 91177308-0d34-0410-b5e6-96231b3b80d8 2010-10-21T19:48:38Z Wesley Peck peckw@wesleypeck.com 2010-10-21T19:48:38Z urn:sha1:4da992aebada7445ef68a7b6b94676dd26e9d537 mostly based on the ARM AsmParser at this time and is not particularly functional. Changed the MBlaze data layout from: "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32" to: "E-p:32:32:32-i8:8:8-i16:16:16" because the MicroBlaze doesn't have i64, f64, v64, or v128 data types. Cleaned up the MBlaze source code: 1. The floating point register class has been removed. The MicroBlaze does not have floating point registers. Floating point values are simply stored in integer registers. 2. Renaming the CPURegs register class to GPR to reflect the standard naming. 3. Removing a lot of stale code from AsmPrinter after the conversion to InstPrinter. 4. Simplified sign extended loads by marking them as expanded in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117054 91177308-0d34-0410-b5e6-96231b3b80d8 2010-10-21T03:57:26Z Wesley Peck peckw@wesleypeck.com 2010-10-21T03:57:26Z urn:sha1:4e9141fd4c0040cd7d4d830211f7d27fd98e9338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116993 91177308-0d34-0410-b5e6-96231b3b80d8