llvm/lib/Target/IA64, branch release_23http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/IA64?h=release_232008-04-12T04:36:06ZDrop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal2008-04-12T04:36:06ZDan Gohmangohman@apple.com2008-04-12T04:36:06Zurn:sha1:707e0184233f27e0e9f9aee0309f2daab8cfe7f8
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.
Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.
This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.
Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.
This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.2008-03-31T20:40:39ZEvan Chengevan.cheng@apple.com2008-03-31T20:40:39Zurn:sha1:ca1267c02b025cc719190b05f9e1a5d174a9caf7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.2008-03-15T00:03:38ZEvan Chengevan.cheng@apple.com2008-03-15T00:03:38Zurn:sha1:da47e6e0d003c873da960361549e57ee4617c301
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
Use SDTNone instead of duplicating it.2008-03-13T23:07:40ZDan Gohmangohman@apple.com2008-03-13T23:07:40Zurn:sha1:704df9fcbddd8bd6f358bef688ef51f8540dce4d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48346 91177308-0d34-0410-b5e6-96231b3b80d8
Use PassManagerBase instead of FunctionPassManager for functions2008-03-11T22:29:46ZDan Gohmangohman@apple.com2008-03-11T22:29:46Zurn:sha1:bfae83139dcb4fffd50b939e1b1224b0126f04d4
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48256 91177308-0d34-0410-b5e6-96231b3b80d8
- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.2008-03-10T23:49:09ZScott Michelscottm@aero.org2008-03-10T23:49:09Zurn:sha1:405fba12ce4874e0b599b19168b1d29d1c64ffab
- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48197 91177308-0d34-0410-b5e6-96231b3b80d8
Default ISD::PREFETCH to expand.2008-03-10T19:38:10ZEvan Chengevan.cheng@apple.com2008-03-10T19:38:10Zurn:sha1:d2cde68855125b6815b1575f29cd96927614b0cd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48169 91177308-0d34-0410-b5e6-96231b3b80d8
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's2008-03-10T15:42:14ZScott Michelscottm@aero.org2008-03-10T15:42:14Zurn:sha1:5b8f82e35b51bf007de07a7ca9347d804084ddf8
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.ll2008-03-09T20:12:44ZChris Lattnersabre@nondot.org2008-03-09T20:12:44Zurn:sha1:68a0d0984db8975ad9c7abbfedd80ef8427e797a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48118 91177308-0d34-0410-b5e6-96231b3b80d8
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.2008-03-08T00:58:38ZEvan Chengevan.cheng@apple.com2008-03-08T00:58:38Zurn:sha1:27b7db549e4c5bff4579d209304de5628513edeb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8