llvm/lib/Target/Hexagon, branch testing http://llvm.org https://git.amat.us/llvm/atom/lib/Target/Hexagon?h=testing 2013-03-14T19:08:03Z Hexagon: Removed asserts regarding alignment and offset. 2013-03-14T19:08:03Z Jyotsna Verma jverma@codeaurora.org 2013-03-14T19:08:03Z urn:sha1:cec50e6da221edeef922a5d5f85081ba66b08dab We are warning the user about the alignment, so we should not assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8 Cleanup #includes. 2013-03-10T13:11:23Z Jakub Staszak kubastaszak@gmail.com 2013-03-10T13:11:23Z urn:sha1:760fa5dc8022dcf6982969c26ef566dfbeea979c git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176787 91177308-0d34-0410-b5e6-96231b3b80d8 DAGCombiner: Use correct value type for checking legality of BR_CC v3 2013-03-08T15:36:57Z Tom Stellard thomas.stellard@amd.com 2013-03-08T15:36:57Z urn:sha1:3ef5383b3537a420c5e2ab3e657c378e5185549d LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Add patterns for zero extended loads from i1->i64. 2013-03-08T14:15:15Z Jyotsna Verma jverma@codeaurora.org 2013-03-08T14:15:15Z urn:sha1:86df21767a0465f9044929e9bfc829fb34d99c19 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Handle i8, i16 and i1 Var Args. 2013-03-07T20:28:34Z Jyotsna Verma jverma@codeaurora.org 2013-03-07T20:28:34Z urn:sha1:a4dd8d67320d86ca7dfd88cb3d0c189cab713a88 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176647 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Add support to lower block address. 2013-03-07T19:10:28Z Jyotsna Verma jverma@codeaurora.org 2013-03-07T19:10:28Z urn:sha1:b6716187ca8cc33817fb7446d9d9bdcb708c3f35 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8 reverting patch 176508. 2013-03-05T20:29:23Z Jyotsna Verma jverma@codeaurora.org 2013-03-05T20:29:23Z urn:sha1:0d44328ce89b19602074676378a92c3b36bb0d83 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Add support for lowering block address. 2013-03-05T19:37:46Z Jyotsna Verma jverma@codeaurora.org 2013-03-05T19:37:46Z urn:sha1:c34f17140fb3bc66ba48af9beb5060d4064b353f git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Expand addc, adde, subc and sube. 2013-03-05T19:04:47Z Jyotsna Verma jverma@codeaurora.org 2013-03-05T19:04:47Z urn:sha1:18daead3ff41902a61ff3344cfa77ac8aba5586d git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Use MO operand flags to mark constant extended instructions. 2013-03-05T18:51:42Z Jyotsna Verma jverma@codeaurora.org 2013-03-05T18:51:42Z urn:sha1:9feabc23b39d90f8bf9ab5ac23f5a7f8af71480a git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176500 91177308-0d34-0410-b5e6-96231b3b80d8