llvm/lib/Target/CellSPU, branch release_30 http://llvm.org https://git.amat.us/llvm/atom/lib/Target/CellSPU?h=release_30 2011-10-13T11:40:03Z Mark 'branch indirect' instruction as an indirect branch. 2011-10-13T11:40:03Z Kalle Raiskila kalle.raiskila@nokia.com 2011-10-13T11:40:03Z urn:sha1:898f336c515e7af607d1ee05a98319912894f24f Not having it confused assembly printing of jumptables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141862 91177308-0d34-0410-b5e6-96231b3b80d8 Fix a iterator out of bounds error, that triggers rarely. 2011-10-11T12:55:18Z Kalle Raiskila kalle.raiskila@nokia.com 2011-10-11T12:55:18Z urn:sha1:56354d48bb937cbb23736d24d9ca4d7a0fcc97e0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141665 91177308-0d34-0410-b5e6-96231b3b80d8 Build system infrastructure for multiple tblgens. 2011-10-06T01:51:51Z Peter Collingbourne peter@pcc.me.uk 2011-10-06T01:51:51Z urn:sha1:de8f33c199f3bf2049b0b732169f2bd8717469c6 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8 Set operation actions to legal types only. 2011-10-04T12:05:35Z Nadav Rotem nadav.rotem@intel.com 2011-10-04T12:05:35Z urn:sha1:34804c4f4793abbcb908c79fe9512c03090d8520 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141075 91177308-0d34-0410-b5e6-96231b3b80d8 Operations should be custom lowered only if their type is legal. 2011-10-04T10:03:32Z Nadav Rotem nadav.rotem@intel.com 2011-10-04T10:03:32Z urn:sha1:e8783096d2d7778e02b19794c01212724c167689 Test: CellSPU/v2i32.ll when running with -promote-elements git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141074 91177308-0d34-0410-b5e6-96231b3b80d8 Add codegen support for vector select (in the IR this means a select 2011-09-06T19:07:46Z Duncan Sands baldrick@free.fr 2011-09-06T19:07:46Z urn:sha1:28b77e968d2b01fc9da724762bd8ddcd80650e32 with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8 Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction. 2011-09-02T10:05:01Z Kalle Raiskila kalle.raiskila@nokia.com 2011-09-02T10:05:01Z urn:sha1:989621f1f8356c977d7578252422de1b65d24587 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139004 91177308-0d34-0410-b5e6-96231b3b80d8 Fix typos in SPUMCTargetDesc.h 2011-08-30T07:27:02Z James Molloy james.molloy@arm.com 2011-08-30T07:27:02Z urn:sha1:e7815c22fc1f6beb38500745904209d2c6bbf3fd Patch supplied by Liu (projlc@gmail.com) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138799 91177308-0d34-0410-b5e6-96231b3b80d8 Don't insert branch hint lables that are never used. 2011-08-26T10:14:56Z Kalle Raiskila kalle.raiskila@nokia.com 2011-08-26T10:14:56Z urn:sha1:54f8a9f54dfa39275f6fd277440b233891069283 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138630 91177308-0d34-0410-b5e6-96231b3b80d8 Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24T18:08:43Z Evan Cheng evan.cheng@apple.com 2011-08-24T18:08:43Z urn:sha1:3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8