llvm/lib/Target/Alpha, branch release_22http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/Alpha?h=release_222008-01-15T22:02:54Zrename SDTRet -> SDTNone.2008-01-15T22:02:54ZChris Lattnersabre@nondot.org2008-01-15T22:02:54Zurn:sha1:48be23cd65313b055ca80acb843ed244b18cd980
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
rename MachineInstr::setInstrDescriptor -> setDesc2008-01-11T18:10:50ZChris Lattnersabre@nondot.org2008-01-11T18:10:50Zurn:sha1:5080f4d9919d39b367891dc51e739c571a66036c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45871 91177308-0d34-0410-b5e6-96231b3b80d8
get def use info more correct.2008-01-10T05:12:37ZChris Lattnersabre@nondot.org2008-01-10T05:12:37Zurn:sha1:9b37aaf04c633c68c9ef09d3991d9acfbef9f754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
remove MachineOpCode typedef.2008-01-07T02:48:55ZChris Lattnersabre@nondot.org2008-01-07T02:48:55Zurn:sha1:cc8cd0cbf12c12916d4b38ef0de5be5501c8270e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
Move even more functionality from MRegisterInfo into TargetInstrInfo.2008-01-07T01:35:02ZOwen Andersonresistor@mac.com2008-01-07T01:35:02Zurn:sha1:43dbe05279b753aabda571d9c83eaeb36987001a
Some day I'll get it all moved over...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.2008-01-06T23:38:27ZChris Lattnersabre@nondot.org2008-01-06T23:38:27Zurn:sha1:834f1ce0312e3d00d836f9560cb63182c2c4570f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
Change the 'isStore' inferrer to look for 'SDNPMayStore' 2008-01-06T06:44:58ZChris Lattnersabre@nondot.org2008-01-06T06:44:58Zurn:sha1:c8478d8b12c2d7e4cea32d0c9940f5cac2baa4dd
instead of "ISD::STORE". This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores). This allows us to remove
more explicit isStore flags from the .td files.
Finally, add a warning for when a .td file contains an explicit
isStore and tblgen is able to infer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
Change MachineRelocation::DoesntNeedFnStub to NeedStub. This fields will be used2008-01-03T02:56:28ZEvan Chengevan.cheng@apple.com2008-01-03T02:56:28Zurn:sha1:02aabbf96b1f22144afe2bec8ad480a9b803f6b8
for non-function GV relocations that require function address stubs (e.g. Mac OS X in non-static mode).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45527 91177308-0d34-0410-b5e6-96231b3b80d8
Move some more instruction creation methods from RegisterInfo into InstrInfo.2008-01-01T21:11:32ZOwen Andersonresistor@mac.com2008-01-01T21:11:32Zurn:sha1:f6372aa1cc568df19da7c5023e83c75aa9404a07
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a problem where lib/Target/TargetInstrInfo.h would include and use2008-01-01T01:03:04ZChris Lattnersabre@nondot.org2008-01-01T01:03:04Zurn:sha1:641055225092833197efe8e5bce01d50bcf1daae
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8