llvm/lib/Target/ARM, branch stable

ARM Scheduler Model: Add resources instructions, map resources in subtargets

2013-04-01T13:07:05Z

Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178460 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the old CodePlacementOpt pass.

2013-03-29T17:14:24Z

It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8

Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.

2013-03-28T19:22:28Z

They should always be zero-extended, not sign extended. Added test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8

Testing commit access to llvm. Remove two lines of whitespace from the Thumb README.

2013-03-28T18:26:15Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178256 91177308-0d34-0410-b5e6-96231b3b80d8

Enabling the generation of dependency breakers for partial updates on Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32.

2013-03-27T12:38:44Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178134 91177308-0d34-0410-b5e6-96231b3b80d8

Revert ARM Scheduler Model: Add resources instructions, map resources

2013-03-26T15:14:04Z

This reverts commit r177968. It is causing failures in a local build bot. "fatal error: error in backend: Expected a variant SchedClass" Original commit message: Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178028 91177308-0d34-0410-b5e6-96231b3b80d8

Patch by Gordon Keiser!

2013-03-26T13:58:53Z

If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8

ARM Scheduler Model: Add resources instructions, map resources in subtargets

2013-03-26T02:01:42Z

Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177968 91177308-0d34-0410-b5e6-96231b3b80d8

ARM Scheduler Model: Partial implementation of the new machine scheduler model

2013-03-26T02:01:39Z

This is very much work in progress. Please send me a note if you start to depend on the added abstract read/write resources. They are subject to change until further notice. The old itinerary is still the default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177967 91177308-0d34-0410-b5e6-96231b3b80d8

[arm load/store optimizer] When trying to merge a base update load/store, make

2013-03-25T16:29:20Z

sure the base register and would-be writeback register don't conflict for stores. This was already being done for loads. Unfortunately, it is rather difficult to create a test case for this issue. It was exposed in 450.soplex at LTO and requires unlucky register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177874 91177308-0d34-0410-b5e6-96231b3b80d8