llvm/lib/Target/ARM, branch release_32 http://llvm.org https://git.amat.us/llvm/atom/lib/Target/ARM?h=release_32 2012-11-10T02:09:05Z Disable the Thumb no-return call optimization: 2012-11-10T02:09:05Z Evan Cheng evan.cheng@apple.com 2012-11-10T02:09:05Z urn:sha1:b341fac05a890272024dcc5c7e47d10b22d62b92 mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8 Add ARM TARGET2 relocation. The testcase will follow with actualy use-case. 2012-11-09T20:20:12Z Anton Korobeynikov asl@math.spbu.ru 2012-11-09T20:20:12Z urn:sha1:12cfa119600418d31ceb748d077b3e6f7057a22a Based on the patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167633 91177308-0d34-0410-b5e6-96231b3b80d8 Revert r167620; this can be implemented using an existing CL option. 2012-11-09T18:25:27Z Chad Rosier mcrosier@apple.com 2012-11-09T18:25:27Z urn:sha1:b3235b128f383559a7a9b9119896e406b347879c git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8 Add support for -mstrict-align compiler option for ARM targets. 2012-11-09T17:29:38Z Chad Rosier mcrosier@apple.com 2012-11-09T17:29:38Z urn:sha1:d054eda44114df411a2749e7b6b85d27509a0af1 rdar://12340498 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8 Recommit modified r167540. 2012-11-08T09:51:45Z Amara Emerson amara.emerson@arm.com 2012-11-08T09:51:45Z urn:sha1:214fd3d2449738bbe0215dce24406dc29d9e49f7 Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167574 91177308-0d34-0410-b5e6-96231b3b80d8 Revert r167540 until regression tests are updated. 2012-11-07T18:57:14Z Amara Emerson amara.emerson@arm.com 2012-11-07T18:57:14Z urn:sha1:162d91c1e0bf5c14e2838dd623b3e054e7537de6 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167545 91177308-0d34-0410-b5e6-96231b3b80d8 Improve ARM build attribute emission for architectures types. 2012-11-07T18:01:03Z Amara Emerson amara.emerson@arm.com 2012-11-07T18:01:03Z urn:sha1:19a1fcf8683a2a459a8aac93c1b4d1bf63b018fb This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167540 91177308-0d34-0410-b5e6-96231b3b80d8 [arm fast-isel] Appease the machine verifier by using the proper register 2012-11-07T00:13:01Z Chad Rosier mcrosier@apple.com 2012-11-07T00:13:01Z urn:sha1:6aa6e5a2852ad5c83cef5eb52f62f9267e3511ea classes. For my test case the number of errors drop from 356 to 21. Part of rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167508 91177308-0d34-0410-b5e6-96231b3b80d8 Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all 2012-11-06T23:05:24Z Chad Rosier mcrosier@apple.com 2012-11-06T23:05:24Z urn:sha1:e7bd51980a1341fb60322e5922cfcc0c9b92b165 registers. Previously, the register we being marked as implicitly defined, but not killed. In some cases this would cause the register scavenger to spill a dead register. Also, use an empty register mask to simplify the logic and to reduce the memory footprint. rdar://12592448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8 Vext Lowering was missing opportunities 2012-11-02T21:32:17Z Quentin Colombet qcolombet@apple.com 2012-11-02T21:32:17Z urn:sha1:43934aee71746576b6e16663f382401b8693c83a git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167318 91177308-0d34-0410-b5e6-96231b3b80d8