llvm/lib/Target/ARM, branch release_31 http://llvm.org https://git.amat.us/llvm/atom/lib/Target/ARM?h=release_31 2012-05-01T08:28:53Z Merging r155902: 2012-05-01T08:28:53Z Bill Wendling isanbard@gmail.com 2012-05-01T08:28:53Z urn:sha1:1fb5af610fbbf5740d8176d2d9b57fb4f95321e3 ------------------------------------------------------------------------ r155902 | void | 2012-05-01 01:27:43 -0700 (Tue, 01 May 2012) | 7 lines Change the PassManager from a reference to a pointer. The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_31@155903 91177308-0d34-0410-b5e6-96231b3b80d8 Added support for disassembling unpredictable swp/swpb ARM instructions. 2012-04-18T14:18:57Z Silviu Baranga silviu.baranga@arm.com 2012-04-18T14:18:57Z urn:sha1:35ee7d28a69173ca0c11fb6b3271518bf4c5bff6 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8 Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors. 2012-04-18T14:09:07Z Silviu Baranga silviu.baranga@arm.com 2012-04-18T14:09:07Z urn:sha1:6b9f97dd892b0d61d8a1f0ee4f837058f2ca4552 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8 Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. 2012-04-18T13:12:50Z Silviu Baranga silviu.baranga@arm.com 2012-04-18T13:12:50Z urn:sha1:fa1ebc6abe95b79b7f82030eea53586a8704eb7e git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8 Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction. 2012-04-18T13:02:55Z Silviu Baranga silviu.baranga@arm.com 2012-04-18T13:02:55Z urn:sha1:e546c4c9c3004274c8e275e8303ca078b794bf28 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8 Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler. 2012-04-18T12:48:43Z Silviu Baranga silviu.baranga@arm.com 2012-04-18T12:48:43Z urn:sha1:9e71231309e8924b89aa94ca86cae883db1d2916 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8 Typo. 2012-04-17T21:48:36Z Chad Rosier mcrosier@apple.com 2012-04-17T21:48:36Z urn:sha1:3f5966b85ea572002bfd0bb2f7c371ed087ae260 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154953 91177308-0d34-0410-b5e6-96231b3b80d8 Remove unused CCIfSubtarget. 2012-04-17T11:29:05Z Jay Foad jay.foad@gmail.com 2012-04-17T11:29:05Z urn:sha1:ef1a3a25b3398768b9fad5526782675b1a8c128f git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154921 91177308-0d34-0410-b5e6-96231b3b80d8 Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON. 2012-04-17T08:18:00Z James Molloy james.molloy@arm.com 2012-04-17T08:18:00Z urn:sha1:72aadc057c3fb92b5ccbc4c856306abd3b9d3b83 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154915 91177308-0d34-0410-b5e6-96231b3b80d8 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 2012-04-17T00:49:27Z Kevin Enderby enderby@apple.com 2012-04-17T00:49:27Z urn:sha1:c5a2a33938182ccc5a1a94f7e1e2b3fdaff6a8b1 instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8