llvm/lib/Target/ARM, branch release_27

Merge 99043 from mainline.

2010-03-30T18:35:26Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_27@99907 91177308-0d34-0410-b5e6-96231b3b80d8

Initial bits of ARMv4-only support.

2010-03-06T19:39:36Z

Patch by John Tytgat! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb1 epilogue code generation needs to take into account that callee-saved

2010-03-06T03:28:39Z

registers may be restored via a pop instruction, not just a tRestore. This fixes nightly test 471.omnetep for Thumb1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97867 91177308-0d34-0410-b5e6-96231b3b80d8

Trivial comment change.

2010-03-05T01:45:46Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97776 91177308-0d34-0410-b5e6-96231b3b80d8

Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version

2010-03-04T22:24:41Z

of either sxtb16 or uxtb16, and the unified syntax does not specify ".w". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8

pr6478: The frame pointer spill frame index is only defined when there is a

2010-03-04T21:42:36Z

frame pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97755 91177308-0d34-0410-b5e6-96231b3b80d8

pr6480: Don't try producing ld/st-multiple instructions when the address is

2010-03-04T21:04:38Z

an undef value. This is only going to come up for bugpoint-reduced tests -- correct programs will not access memory at undefined addresses -- so it's not worth the effort of doing anything more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97745 91177308-0d34-0410-b5e6-96231b3b80d8

Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload

2010-03-04T17:40:44Z

Instruction (PLI) for disassembly only. According to A8.6.120 PLI (immediate, literal), for example, different instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"]. The disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97731 91177308-0d34-0410-b5e6-96231b3b80d8

Modified the asm string of 16-bit Thumb MUL instruction so that it prints:

2010-03-03T23:15:43Z

MULS , , according to A8.6.105 MUL Encoding T1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97675 91177308-0d34-0410-b5e6-96231b3b80d8

Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,

2010-03-03T18:45:36Z

and STRHT for disassembly only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97655 91177308-0d34-0410-b5e6-96231b3b80d8