llvm/lib/Target/ARM/Makefile, branch release_33http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/ARM/Makefile?h=release_332012-12-19T19:55:47ZRemove edis - the enhanced disassembler. Fixes PR14654.2012-12-19T19:55:47ZRoman Divackyrdivacky@freebsd.org2012-12-19T19:55:47Zurn:sha1:759e3fa641d0ad01012d16d913015c9f69c8d2ab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
Don't continue generating the old-style decoder file.2011-08-09T21:30:29ZOwen Andersonresistor@mac.com2011-08-09T21:30:29Zurn:sha1:ad0d36b79ff6b13d0acb29d316517f55aab45f4d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137150 91177308-0d34-0410-b5e6-96231b3b80d8
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.2011-08-09T20:55:18ZOwen Andersonresistor@mac.com2011-08-09T20:55:18Zurn:sha1:8d7d2e1238fac58c01ccfb719d0cc5680a079561
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
Use TableGen'erated pseudo lowering for ARM.2011-07-08T17:40:42ZJim Grosbachgrosbach@apple.com2011-07-08T17:40:42Zurn:sha1:53e3fc463e3d9ee840510b08ebd6db17694fa2c5
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
Add ARM MC registry routines.2011-07-06T22:02:34ZEvan Chengevan.cheng@apple.com2011-07-06T22:02:34Zurn:sha1:78a9f138ae95458bf6d922f38706eed045691d5a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134547 91177308-0d34-0410-b5e6-96231b3b80d8
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.2011-07-01T22:36:09ZEvan Chengevan.cheng@apple.com2011-07-01T22:36:09Zurn:sha1:385e930d55f3ecd3c9538823dfa5896a12461845
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc2011-06-28T20:07:07ZEvan Chengevan.cheng@apple.com2011-06-28T20:07:07Zurn:sha1:22fee2dff4c43b551aefa44a96ca74fcade6bfac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc2011-06-27T18:32:37ZEvan Chengevan.cheng@apple.com2011-06-27T18:32:37Zurn:sha1:73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42
into XXXGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
Starting to refactor Target to separate out code that's needed to fully describe2011-06-24T01:44:41ZEvan Chengevan.cheng@apple.com2011-06-24T01:44:41Zurn:sha1:a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
Teach ARM Target to use the tblgen support for generating an MC'ized2010-11-03T23:52:49ZJim Grosbachgrosbach@apple.com2010-11-03T23:52:49Zurn:sha1:806e80ef42bdb416f409142a1ff1d4e8752baac8
CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118209 91177308-0d34-0410-b5e6-96231b3b80d8