llvm/lib/Target/ARM/Disassembler, branch release_32http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/ARM/Disassembler?h=release_322012-10-29T23:27:20ZFix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target2012-10-29T23:27:20ZKevin Enderbyenderby@apple.com2012-10-29T23:27:20Zurn:sha1:445ba85b8d7bc8fb4689ca22131cadc80a034705
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a bug where a 32-bit address with the high bit does not get symbolicated2012-10-18T21:49:18ZKevin Enderbyenderby@apple.com2012-10-18T21:49:18Zurn:sha1:88d12663abdac344f312b09edfe4934143436132
because the value is incorrectly being signed extended when passed to
SymbolLookUp().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166234 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the handling of edge cases in ARM shifted operands.2012-09-22T11:18:12ZTim NorthoverTim.Northover@arm.com2012-09-22T11:18:12Zurn:sha1:93c7c449a1351542fa5a275587187154dbedb8e0
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
Diagnose invalid alignments on duplicating VLDn instructions.2012-09-06T15:27:12ZTim NorthoverTim.Northover@arm.com2012-09-06T15:27:12Zurn:sha1:24b9f258f194c5e472bf133f9bbf5ca26ad500d3
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.2012-09-06T15:17:49ZTim NorthoverTim.Northover@arm.com2012-09-06T15:17:49Zurn:sha1:eae1d34029c159306ce4a0472294de6cf9baedac
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
Fix integer undefined behavior due to signed left shift overflow in LLVM.2012-08-24T23:29:28ZRichard Smithrichard-llvm@metafoo.co.uk2012-08-24T23:29:28Zurn:sha1:1144af3c9b4da48cd581156e05b24261c8de366a
Reviewed offline by chandlerc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unnecessary include of ARMGenInstrInfo.inc.2012-08-17T06:21:09ZCraig Toppercraig.topper@gmail.com2012-08-17T06:21:09Zurn:sha1:960fb7437003dcb96c6af093e2d55e06e4c8bd43
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162086 91177308-0d34-0410-b5e6-96231b3b80d8
Switch the fixed-length disassembler to be table-driven.2012-08-14T19:06:05ZJim Grosbachgrosbach@apple.com2012-08-14T19:06:05Zurn:sha1:fc1a161d76f5cc0204bed3bce3e27cf36ac76d22
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.
As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:
Time to compile at -O2 (averaged w/ hot caches):
Previous: 35.5s
New: 8.9s
TEXT size:
Previous: 447,251
New: 297,661
Builds in 25% of the time previously required and generates code 66% of
the size.
Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.2012-08-02T08:29:50ZJiangning Liujiangning.liu@arm.com2012-08-02T08:29:50Zurn:sha1:fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.2012-08-02T08:21:27ZJiangning Liujiangning.liu@arm.com2012-08-02T08:21:27Zurn:sha1:c1b7ca5ba28ded2d83ae534c8e072c2538d43295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8