llvm/lib/Target/ARM/Disassembler, branch release_31 http://llvm.org https://git.amat.us/llvm/atom/lib/Target/ARM/Disassembler?h=release_31 2012-04-18T14:18:57Z Added support for disassembling unpredictable swp/swpb ARM instructions. 2012-04-18T14:18:57Z Silviu Baranga silviu.baranga@arm.com 2012-04-18T14:18:57Z urn:sha1:35ee7d28a69173ca0c11fb6b3271518bf4c5bff6 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8 Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. 2012-04-18T13:12:50Z Silviu Baranga silviu.baranga@arm.com 2012-04-18T13:12:50Z urn:sha1:fa1ebc6abe95b79b7f82030eea53586a8704eb7e git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) 2012-04-17T00:49:27Z Kevin Enderby enderby@apple.com 2012-04-17T00:49:27Z urn:sha1:c5a2a33938182ccc5a1a94f7e1e2b3fdaff6a8b1 instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8 Fix a few more places in the ARM disassembler so that branches get 2012-04-12T23:13:34Z Kevin Enderby enderby@apple.com 2012-04-12T23:13:34Z urn:sha1:2a7d3a93735f97c2a4cabcc08a88d702c28cb0d4 symbolic operands added when using the C disassembler API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154628 91177308-0d34-0410-b5e6-96231b3b80d8 Fixed a case of ARM disassembly getting an assert on a bad encoding 2012-04-11T22:40:17Z Kevin Enderby enderby@apple.com 2012-04-11T22:40:17Z urn:sha1:b318cc16c9e959adb96294b3aa4940e74f68dde3 of a VST instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8 Fix ARM disassembly of VLD instructions with writebacks.  And add test a case 2012-04-11T00:25:40Z Kevin Enderby enderby@apple.com 2012-04-11T00:25:40Z urn:sha1:a69da35c127dd7e35ae6216d965670643dc55bb6 for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8 ARMDisassembler: drop bogus dependency on ARMCodeGen 2012-04-03T15:48:14Z Dylan Noblesmith nobled@dreamwidth.org 2012-04-03T15:48:14Z urn:sha1:75e3b7fb8fdf069b6f9f1e1db9634ca5701cbe96 And indirectly, a dependency on most of the core LLVM optimization libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153957 91177308-0d34-0410-b5e6-96231b3b80d8 Remove unnecessary llvm:: qualifications 2012-03-27T07:21:54Z Craig Topper craig.topper@gmail.com 2012-03-27T07:21:54Z urn:sha1:c89c744b69cecac576317a98322fd295e36e9886 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 2012-03-22T14:14:49Z Silviu Baranga silviu.baranga@arm.com 2012-03-22T14:14:49Z urn:sha1:6fe310e1555dedba2b36dedae9a88eb900ad1804 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8 Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 2012-03-22T13:24:43Z Silviu Baranga silviu.baranga@arm.com 2012-03-22T13:24:43Z urn:sha1:b7c2ed66642b141a768b3074c465eba9d98665d8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8