llvm/lib/Target/ARM/Disassembler, branch release_30http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/ARM/Disassembler?h=release_302011-10-14T20:50:26ZFix a non-firing assert. Change:2011-10-14T20:50:26ZRichard Trieurtrieu@google.com2011-10-14T20:50:26Zurn:sha1:8223e45dff0f368ee40242f9e81f09b40e081756
assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
Fix undefined shift. Patch by Ahmed Charles.2011-10-13T23:36:06ZEli Friedmaneli.friedman@gmail.com2011-10-13T23:36:06Zurn:sha1:ecb830e45c216209f4a8b95d687f1ef4e9185bee
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8
SETEND is not allowed in an IT block.2011-10-13T17:58:39ZOwen Andersonresistor@mac.com2011-10-13T17:58:39Zurn:sha1:c18e940c5a1c050701594ee2b356cd40249505a3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8
ARM addrmode5 represents the 'U' bit of the encoding backwards.2011-10-12T21:59:02ZJim Grosbachgrosbach@apple.com2011-10-12T21:59:02Zurn:sha1:81b2928d80047cb6c8ae0048185742abae1d9dfa
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8
Thumb2 assembly parsing and encoding for LDC/STC.2011-10-12T20:54:17ZJim Grosbachgrosbach@apple.com2011-10-12T20:54:17Zurn:sha1:c66e7afcf2810a2c1ebf08514eaf45c478e5ff67
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
addrmode2 is gone from these, so no need for the reg0 operand.2011-10-12T18:11:24ZJim Grosbachgrosbach@apple.com2011-10-12T18:11:24Zurn:sha1:b0786b33fa9090adee9a30796ead7969f948f4cd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.2011-10-06T23:33:11ZOwen Andersonresistor@mac.com2011-10-06T23:33:11Zurn:sha1:7011eee9b509f3a0f95a75f68787384f31ea3e01
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
Adding back support for printing operands symbolically to ARM's new disassembler2011-10-04T22:44:48ZKevin Enderbyenderby@apple.com2011-10-04T22:44:48Zurn:sha1:9e5887b17e634b98f7c1cf0ee4f25c218097d08e
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.2011-09-30T00:50:06ZJim Grosbachgrosbach@apple.com2011-09-30T00:50:06Zurn:sha1:4ebbf7b8a8e80532bd2ddf7209e62689c1698a96
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.2011-09-26T21:06:22ZOwen Andersonresistor@mac.com2011-09-26T21:06:22Zurn:sha1:0afa0094afdfe589f407feb76948f273b414b278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8