llvm/lib/Target/ARM/Disassembler, branch release_28http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/ARM/Disassembler?h=release_282010-09-08T10:09:17Z$ svn merge -c 113255 https://llvm.org/svn/llvm-project/llvm/trunk2010-09-08T10:09:17ZBill Wendlingisanbard@gmail.com2010-09-08T10:09:17Zurn:sha1:1113b52df056ed23dbe954c732bcd820c2375bf7
--- Merging r113255 into '.':
U lib/Target/ARM/Disassembler/ARMDisassemblerCore.h
$ svn merge -c 113345 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r113345 into '.':
U lib/Target/ARM/Disassembler/ARMDisassembler.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_28@113353 91177308-0d34-0410-b5e6-96231b3b80d8
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like2010-08-27T23:18:17ZBob Wilsonbob.wilson@apple.com2010-08-27T23:18:17Zurn:sha1:d4bfd54ec2947e73ab152c3c548e4dd4beb700ba
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
explicitly handle no-op cases for clarity. Fixes clang warning.2010-08-17T18:00:41ZJim Grosbachgrosbach@apple.com2010-08-17T18:00:41Zurn:sha1:3edb90492727f60683181672201fd811101ea0d7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111260 91177308-0d34-0410-b5e6-96231b3b80d8
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid2010-08-17T17:23:19ZBob Wilsonbob.wilson@apple.com2010-08-17T17:23:19Zurn:sha1:f955f290c949ff0df7d23cec055efcc4ffeb35d1
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
Move the Thumb2 SSAT and USAT optional shift operator out of the2010-08-13T21:48:10ZBob Wilsonbob.wilson@apple.com2010-08-13T21:48:10Zurn:sha1:38aa2871fc7a37f7a6854744e71fc366ba12888a
instruction opcode. This fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor the code for disassembling Thumb2 saturate instructions along the2010-08-13T19:04:21ZBob Wilsonbob.wilson@apple.com2010-08-13T19:04:21Zurn:sha1:6daf2a254b89bc039f9d58c38e2158a1896d4695
same lines as the change I made for ARM saturate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111029 91177308-0d34-0410-b5e6-96231b3b80d8
Cleaned up the for-disassembly-only entries in the arm instruction table so that2010-08-12T20:46:17ZJohnny Chenjohnny.chen@apple.com2010-08-12T20:46:17Zurn:sha1:1adc40cac314b0a77b790b094bca146a3a868452
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td2010-08-12T01:40:54ZJohnny Chenjohnny.chen@apple.com2010-08-12T01:40:54Zurn:sha1:270159fcc21e06c67aa571d10d2b22d41d9a751a
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.2010-08-11T23:35:12ZJohnny Chenjohnny.chen@apple.com2010-08-11T23:35:12Zurn:sha1:7def14f40f0b47551e2d66ec2f140a18b5bbbea4
Added two test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
Move the ARM SSAT and USAT optional shift amount operand out of the2010-08-11T23:10:46ZBob Wilsonbob.wilson@apple.com2010-08-11T23:10:46Zurn:sha1:eaf1c98a7c38444d41d1c6dc2074736eec7d452f
instruction opcode. This also fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8