llvm/lib/Target/AArch64, branch stablehttp://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/AArch64?h=stable2013-03-28T14:30:46ZAArch64: implement GICv3 system registers2013-03-28T14:30:46ZTim NorthoverTim.Northover@arm.com2013-03-28T14:30:46Zurn:sha1:42a1b2f0b196633c0327801e810fc98849a00c47
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
Switch to LLVM support function abs64 to keep VS2008 happy.2013-03-27T13:15:08ZTim NorthoverTim.Northover@arm.com2013-03-27T13:15:08Zurn:sha1:fe37e6279ebbb4ba1eede4bcb8dfe732f0bbcb38
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178141 91177308-0d34-0410-b5e6-96231b3b80d8
Allow the register scavenger to spill multiple registers2013-03-22T23:32:27ZHal Finkelhfinkel@anl.gov2013-03-22T23:32:27Zurn:sha1:dc3beb90178fc316f63790812b22201884eaa017
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.
To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.
In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
Silence anonymous type in anonymous union warnings.2013-03-15T00:42:55ZEric Christopherechristo@gmail.com2013-03-15T00:42:55Zurn:sha1:a286fc065a5bc846d73c8407a534a1d3c1d70b59
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8
Move estimateStackSize from ARM into MachineFrameInfo2013-03-14T21:15:20ZHal Finkelhfinkel@anl.gov2013-03-14T21:15:20Zurn:sha1:0cc52c67dbc2e073e3f7f34e05e3e7cd17ba9745
This is a generic function (derived from PEI); moving it into
MachineFrameInfo eliminates a current redundancy between the ARM and AArch64
backends, and will allow it to be used by the PowerPC target code.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: expand sincos operations, we don't support them.2013-03-08T13:55:07ZTim NorthoverTim.Northover@arm.com2013-03-08T13:55:07Zurn:sha1:69fe178f7781fa3c01d013ac7b7858926064f6ca
Patch based on Mans Rullgard's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176688 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: remove post-encoder method from FCMP (immediate) instructions.2013-02-28T14:46:14ZTim NorthoverTim.Northover@arm.com2013-02-28T14:46:14Zurn:sha1:54a1cf75d2b32cd96ec78f61af5c1bed8d81524d
The work done by the post-encoder (setting architecturally unused bits to 0 as
required) can be done by the existing operand that covers the "#0.0". This
removes at least one use of the discouraged PostEncoderMethod uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176261 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: be more careful resorting to inefficient addressing for weak vars.2013-02-28T14:36:31ZTim NorthoverTim.Northover@arm.com2013-02-28T14:36:31Zurn:sha1:6ff20f205b2aa126b268bcada9920f56715161be
If an otherwise weak var is actually defined in this unit, it can't be
undefined at runtime so we can use normal global variable sequences (ADRP/ADD)
to access it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176259 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: don't drop GlobalAddress offset when handling extern_weak decls.2013-02-28T14:36:24ZTim NorthoverTim.Northover@arm.com2013-02-28T14:36:24Zurn:sha1:5366ab21f4595d0e3888b2d23f38469da2465b8d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176258 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: Use cbnz instead of cmp/b.ne pair for atomic operations.2013-02-28T13:52:07ZTim NorthoverTim.Northover@arm.com2013-02-28T13:52:07Zurn:sha1:279b9184c2ff4fea93b198a3519b8cb3a1d8d195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176253 91177308-0d34-0410-b5e6-96231b3b80d8