llvm/lib/CodeGen, branch stablehttp://llvm.orghttps://git.amat.us/llvm/atom/lib/CodeGen?h=stable2013-04-01T18:12:58ZMerge load/store sequences with adresses: base + index + offset2013-04-01T18:12:58ZArnold Schwaighoferaschwaighofer@apple.com2013-04-01T18:12:58Zurn:sha1:f28a29b776b7dc2b97d09c75d69494f862c216b3
We would also like to merge sequences that involve a variable index like in the
example below.
int index = *idx++
int i0 = c[index+0];
int i1 = c[index+1];
b[0] = i0;
b[1] = i1;
By extending the parsing of the base pointer to handle dags that contain a
base, index, and offset we can handle examples like the one above.
The dag for the code above will look something like:
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i8 load %index))))
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i32 add (i32 signextend (i8 load %index))
(i32 1)))))
The code that parses the tree ignores the intermediate sign extensions. However,
if there is a sign extension it needs to be on all indexes.
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (add (i8 load %index)
(i8 1))))
vs
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i32 add (i32 signextend (i8 load %index))
(i32 1)))))
radar://13536387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178483 91177308-0d34-0410-b5e6-96231b3b80d8
DAGCombine: visitXOR can replace a node without returning it, bail out in that case.2013-03-30T21:28:18ZBenjamin Kramerbenny.kra@googlemail.com2013-03-30T21:28:18Zurn:sha1:0b68b758bbb6718fc67423109eeb9df64c711a37
Fixes the crash reported in PR15608.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178429 91177308-0d34-0410-b5e6-96231b3b80d8
Use SmallVectorImpl instead of SmallVector at the uses.2013-03-29T23:34:06ZEric Christopherechristo@gmail.com2013-03-29T23:34:06Zurn:sha1:f7cef7081b2e09b48d47263e391db2390dddf5e8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178386 91177308-0d34-0410-b5e6-96231b3b80d8
Use 12 as the magic number for our abbreviation data and our2013-03-29T20:23:06ZEric Christopherechristo@gmail.com2013-03-29T20:23:06Zurn:sha1:2df938ad713140c352b2d81b49490e337c018891
die values. A lot of DIEs have 10 attributes in C++ code (example
clang), none had more than 12. Seems like a good default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178366 91177308-0d34-0410-b5e6-96231b3b80d8
Move the construction of the skeleton compile unit after the2013-03-29T20:23:02ZEric Christopherechristo@gmail.com2013-03-29T20:23:02Zurn:sha1:c126c3232a7c6c2e2a2ec9477252f1372b14f728
entire original compile unit has been constructed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178365 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the old CodePlacementOpt pass.2013-03-29T17:14:24ZBenjamin Kramerbenny.kra@googlemail.com2013-03-29T17:14:24Zurn:sha1:74a4533a4290b7c6f1fe04a30ca13ec25c529e0a
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a typo2013-03-29T16:34:23ZNadav Rotemnrotem@apple.com2013-03-29T16:34:23Zurn:sha1:975ee54731476ff6541fc42f6a8cd706f3d33f58
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178346 91177308-0d34-0410-b5e6-96231b3b80d8
[fast-isel] Add a preemptive fix for the case where we fail to materialize an2013-03-28T23:04:47ZChad Rosiermcrosier@apple.com2013-03-28T23:04:47Zurn:sha1:7ae3bb83c278e991940d022b7b48d996da408abf
immediate in a register. I don't believe this should ever fail, but I see no
harm in trying to make this code bullet proof.
I've added an assert to ensure my assumtion is correct. If the assertion fires
something is wrong and we should fix it, rather then just silently fall back to
SelectionDAG isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178305 91177308-0d34-0410-b5e6-96231b3b80d8
Fix target-customized spilling in the register scavenger2013-03-27T13:00:56ZHal Finkelhfinkel@anl.gov2013-03-27T13:00:56Zurn:sha1:26998ee794e9b6f9b0bc27d1e273b6b78afce57d
This is a follow-up to r178073 (which should actually make target-customized
spilling work again).
I still don't have a regression test for this (but it would be good to have
one; Thumb 1 and Mips16 use this callback as well).
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178137 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the register scavenger for targets that provide custom spilling2013-03-26T21:20:15ZHal Finkelhfinkel@anl.gov2013-03-26T21:20:15Zurn:sha1:df23a60fa6ce053511388e1bccca5900757e1aac
As pointed out by Richard Sandiford, my recent updates to the register
scavenger broke targets that use custom spilling (because the new code assumed
that if there were no valid spill slots, than spilling would be impossible).
I don't have a test case, but it should be possible to create one for Thumb 1,
Mips 16, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178073 91177308-0d34-0410-b5e6-96231b3b80d8