llvm/lib/CodeGen, branch release_32

Merging r168622: into 3.2 release branch.

2012-11-29T22:11:02Z

Don't use iterator after being erased. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168947 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r168837: into the 3.2 release branch.

2012-11-29T02:35:17Z

Avoid rewriting instructions twice. This could cause miscompilations in targets where sub-register composition is not always idempotent (ARM). git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168849 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r167912: into the 3.2 release branch.

2012-11-26T17:01:12Z

Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168596 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r168320: into 3.2 relase branch.

2012-11-23T20:02:28Z

Handle mixed normal and early-clobber defs on inline asm. PR14376. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168527 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r167855 into 3.2 relase branch

2012-11-19T22:17:54Z

Do not consider a machine instruction that uses and defines the same physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168334 91177308-0d34-0410-b5e6-96231b3b80d8

Fix assertions in updateRegMaskSlots().

2012-11-09T19:18:49Z

The RegMaskSlots contains 'r' slots while NewIdx and OldIdx are 'B' slots. This broke the checks in the assertions. This fixes PR14302. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167625 91177308-0d34-0410-b5e6-96231b3b80d8

Silence GCC warning about falling off the end of a non-void function.

2012-11-09T15:45:22Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167618 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Heuristics based on the machine model.

2012-11-07T07:05:09Z

misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8

misched: handle on-the-fly regpressure queries better for 2-addr

2012-11-07T07:05:05Z

instructions without relying on liveintervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167526 91177308-0d34-0410-b5e6-96231b3b80d8

Add comment describing what's going on here.

2012-11-07T05:19:04Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167525 91177308-0d34-0410-b5e6-96231b3b80d8