<feed xmlns='http://www.w3.org/2005/Atom'>
<title>llvm/lib/CodeGen/SelectionDAG, branch testing</title>
<subtitle>http://llvm.org</subtitle>
<id>https://git.amat.us/llvm/atom/lib/CodeGen/SelectionDAG?h=testing</id>
<link rel='self' href='https://git.amat.us/llvm/atom/lib/CodeGen/SelectionDAG?h=testing'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/'/>
<updated>2013-03-20T23:10:59Z</updated>
<entry>
<title>Make variable name more explicit and eliminate redundant lookup in SDNodeOrdering</title>
<updated>2013-03-20T23:10:59Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2013-03-20T23:10:59Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=93c1fd49d2ca49447e092c4c1c4d5de1005e9e71'/>
<id>urn:sha1:93c1fd49d2ca49447e092c4c1c4d5de1005e9e71</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177600 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>When computing the demanded bits of Load SDNodes, make sure that we are looking at the loaded-value operand and not the ptr result (in case of pre-inc loads).</title>
<updated>2013-03-20T22:53:44Z</updated>
<author>
<name>Nadav Rotem</name>
<email>nrotem@apple.com</email>
</author>
<published>2013-03-20T22:53:44Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=7745175be32cd54e4aa6c9cce6f642f59a34a80f'/>
<id>urn:sha1:7745175be32cd54e4aa6c9cce6f642f59a34a80f</id>
<content type='text'>
rdar://13348420



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177596 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Revert "pre-RA-sched: fix TargetOpcode usage"</title>
<updated>2013-03-20T15:43:00Z</updated>
<author>
<name>Christian Konig</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2013-03-20T15:43:00Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=61aba54f2c0f432179dfaa758bdb2bf1b9929814'/>
<id>urn:sha1:61aba54f2c0f432179dfaa758bdb2bf1b9929814</id>
<content type='text'>
This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02.

The code is obviously wrong, but the trivial fix causes
inefficient code generation on X86. Somebody with more
knowledge of the code needs to take a look here.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Move SDNode order propagation to SDNodeOrdering, which also fixes a missed</title>
<updated>2013-03-20T14:51:01Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2013-03-20T14:51:01Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=fa963a885c074b3b0d6cc2466036297c476f7103'/>
<id>urn:sha1:fa963a885c074b3b0d6cc2466036297c476f7103</id>
<content type='text'>
case of order propagation during isel.

Thanks Owen for the suggestion!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177525 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>pre-RA-sched: fix TargetOpcode usage</title>
<updated>2013-03-20T13:49:22Z</updated>
<author>
<name>Christian Konig</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2013-03-20T13:49:22Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=06091513c283c863296f01cc7c2e86b56bb50d02'/>
<id>urn:sha1:06091513c283c863296f01cc7c2e86b56bb50d02</id>
<content type='text'>
TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177518 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Propagate DAG node ordering during type legalization and instruction selection</title>
<updated>2013-03-20T00:10:32Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2013-03-20T00:10:32Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=d73dc544f5e37e6d58befc71e57da3c132804543'/>
<id>urn:sha1:d73dc544f5e37e6d58befc71e57da3c132804543</id>
<content type='text'>
A node's ordering is only propagated during legalization if (a) the new node does
not have an ordering (is not a CSE'd node), or (b) the new node has an ordering
that is higher than the node being legalized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Reset some of the target options which affect code generation.</title>
<updated>2013-03-13T22:26:59Z</updated>
<author>
<name>Bill Wendling</name>
<email>isanbard@gmail.com</email>
</author>
<published>2013-03-13T22:26:59Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=4cb1f5f4064f2eec1420dc30bf32ac54bd40e222'/>
<id>urn:sha1:4cb1f5f4064f2eec1420dc30bf32ac54bd40e222</id>
<content type='text'>
This doesn't reset all of the target options within the TargetOptions
object. This is because some of those are ABI-specific and must be determined if
it's okay to change those on the fly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176986 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Avoid generating ISD::SELECT for vector operands to SIGN_EXTEND</title>
<updated>2013-03-12T18:17:18Z</updated>
<author>
<name>Richard Relph</name>
<email>Richard.Relph@amd.com</email>
</author>
<published>2013-03-12T18:17:18Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=1a5c0510ecb029b7e5d04249cdd4e50b97bf1c3f'/>
<id>urn:sha1:1a5c0510ecb029b7e5d04249cdd4e50b97bf1c3f</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176881 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Fix a crasher newly introduced in r176659/r176649, where fast-isel tries to</title>
<updated>2013-03-11T21:44:37Z</updated>
<author>
<name>Nick Lewycky</name>
<email>nicholas@mxc.ca</email>
</author>
<published>2013-03-11T21:44:37Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=33cdfe9f1943418604be5c800800394ae809fc4c'/>
<id>urn:sha1:33cdfe9f1943418604be5c800800394ae809fc4c</id>
<content type='text'>
lower an expect intrinsic that is a constant expression.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176830 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Disable statistics on Release builds and move tests that depend on -stats.</title>
<updated>2013-03-08T22:56:31Z</updated>
<author>
<name>Jan Wen Voung</name>
<email>jvoung@google.com</email>
</author>
<published>2013-03-08T22:56:31Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=fa785cb22d50c657eb08c762d627cd6aa96982f3'/>
<id>urn:sha1:fa785cb22d50c657eb08c762d627cd6aa96982f3</id>
<content type='text'>
Summary:
Statistics are still available in Release+Asserts (any +Asserts builds),
and stats can also be turned on with LLVM_ENABLE_STATS.

Move some of the FastISel stats that were moved under DEBUG()
back out of DEBUG(), since stats are disabled across the board now.

Many tests depend on grepping "-stats" output.  Move those into
a orig_dir/Stats/. so that they can be marked as unsupported
when building without statistics.

Differential Revision: http://llvm-reviews.chandlerc.com/D486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176733 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
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