llvm/lib/CodeGen/SelectionDAG, branch release_30 http://llvm.org https://git.amat.us/llvm/atom/lib/CodeGen/SelectionDAG?h=release_30 2011-10-26T04:25:53Z Merging r143006: 2011-10-26T04:25:53Z Bill Wendling isanbard@gmail.com 2011-10-26T04:25:53Z urn:sha1:ae66c2a154dbdd011e2382e16137493dfb61aa3b ------------------------------------------------------------------------ r143006 | stoklund | 2011-10-25 18:47:48 -0700 (Tue, 25 Oct 2011) | 8 lines Don't use floating point to do an integer's job. This code makes different decisions when compiled into x87 instructions because of different rounding behavior. That caused phase 2/3 miscompares on 32-bit Linux when the phase 1 compiler was built with gcc (using x87), and the phase 2 compiler was built with clang (using SSE). This fixes PR11200. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@143013 91177308-0d34-0410-b5e6-96231b3b80d8 Merging r142350: 2011-10-20T20:28:08Z Bill Wendling isanbard@gmail.com 2011-10-20T20:28:08Z urn:sha1:17b2b19ca7fc1c6b379769b45767edf17d1c4d71 ------------------------------------------------------------------------ r142350 | baldrick | 2011-10-18 05:44:00 -0700 (Tue, 18 Oct 2011) | 3 lines Fix a bunch of unused variable warnings when doing a release build with gcc-4.6. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142609 91177308-0d34-0410-b5e6-96231b3b80d8 Clear out the landing pad to call site map for each function. 2011-10-15T01:00:26Z Bill Wendling isanbard@gmail.com 2011-10-15T01:00:26Z urn:sha1:4ed1fb009543effaeb31547fd1d4795a649c3b93 This isn't put into the 'clear()' method because the information needs to stick around (at least for a little bit) after the selection DAG is built. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142032 91177308-0d34-0410-b5e6-96231b3b80d8 Fix typo. "__sync_fetch_and-xor_4" should be "__sync_fetch_and_xor_4". 2011-10-14T15:53:48Z Jim Grosbach grosbach@apple.com 2011-10-14T15:53:48Z urn:sha1:312b7c950a27f72a811b3fdbed26e2e08eb20c31 Pointed out by George Russell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141956 91177308-0d34-0410-b5e6-96231b3b80d8 Encode register class constreaints in inline asm instructions. 2011-10-12T23:37:29Z Jakob Stoklund Olesen stoklund@2pi.dk 2011-10-12T23:37:29Z urn:sha1:459b74b9644c4741d93fe73adc2b06ca6bdb366d The inline asm operand constraint is initially encoded in the virtual register for the operand, but that register class may change during coalescing, and the original constraint is lost. Encode the original register class as part of the flag word for each inline asm operand. This makes it possible to recover the actual constraint required by inline asm, just like we can for normal instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141833 91177308-0d34-0410-b5e6-96231b3b80d8 Use a utility from MathExtras to clarify a check and avoid undefined behavior. Based on patch by Ahmed Charles. 2011-10-12T22:46:45Z Eli Friedman eli.friedman@gmail.com 2011-10-12T22:46:45Z urn:sha1:5c75af6eb72bd74bc35f46e5037dd5646e04f3b6 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141829 91177308-0d34-0410-b5e6-96231b3b80d8 Fix a thinko that Nick noticed. The previous code actually worked as 2011-10-12T15:56:56Z Dan Gohman gohman@apple.com 2011-10-12T15:56:56Z urn:sha1:9e15d658c99c3f0717cb83cc2bd2aa29abdbcdbb intended, but only by accident. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141779 91177308-0d34-0410-b5e6-96231b3b80d8 Use an existing function. 2011-10-12T01:24:51Z Jakob Stoklund Olesen stoklund@2pi.dk 2011-10-12T01:24:51Z urn:sha1:22e8a366adf5a4c78148928ff64e7e00c1088492 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141763 91177308-0d34-0410-b5e6-96231b3b80d8 Formatting. 2011-10-11T22:59:04Z Eric Christopher echristo@apple.com 2011-10-11T22:59:04Z urn:sha1:5ba7b501fd4b88e3fea590499e9464b4b2c153a4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141728 91177308-0d34-0410-b5e6-96231b3b80d8 Add support for legalization of vector SHL/SRA/SRL instructions 2011-10-11T14:36:35Z Nadav Rotem nadav.rotem@intel.com 2011-10-11T14:36:35Z urn:sha1:6fe4e515470a9c2ffa1324261674dde0ede32e72 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141667 91177308-0d34-0410-b5e6-96231b3b80d8