llvm/lib/CodeGen/SelectionDAG, branch release_29http://llvm.orghttps://git.amat.us/llvm/atom/lib/CodeGen/SelectionDAG?h=release_292011-03-11T00:11:06ZMerge r127263 from mainline, fixes PR9427 for 2.9.2011-03-11T00:11:06ZEric Christopherechristo@apple.com2011-03-11T00:11:06Zurn:sha1:5705843fd151b9d701f9cf81edf0497a25aee53a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_29@127437 91177308-0d34-0410-b5e6-96231b3b80d8
Further improvements to pre-RA-sched=list-ilp.2011-03-08T01:51:56ZAndrew Trickatrick@apple.com2011-03-08T01:51:56Zurn:sha1:0bf56c821c454a960afc34cb5746006bc1f9e1a1
This change uses the MaxReorderWindow for both height and depth, which
tends to limit the negative effects of high register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127203 91177308-0d34-0410-b5e6-96231b3b80d8
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.2011-03-07T21:56:36ZCameron Zwarichzwarich@apple.com2011-03-07T21:56:36Zurn:sha1:be2119e8e2bc7006cfd638a24367acbfda625d16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
Use the correct LHS type when determining the legalization of a shift's RHS type.2011-03-07T18:29:47ZOwen Andersonresistor@mac.com2011-03-07T18:29:47Zurn:sha1:6154f6c9292179fab6346ae8336f2ad790b52028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127163 91177308-0d34-0410-b5e6-96231b3b80d8
Typo.2011-03-06T21:13:45ZEric Christopherechristo@apple.com2011-03-06T21:13:45Zurn:sha1:b43034d700004e1fec3ddf177e21ac89478bcc6c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127131 91177308-0d34-0410-b5e6-96231b3b80d8
Disable a couple of experimental heuristics to get the best results from the current implementation of -pre-RA-sched=list-ilp.2011-03-06T00:03:32ZAndrew Trickatrick@apple.com2011-03-06T00:03:32Zurn:sha1:3c6e49504e9a57a4818750fd2520967f84634eac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127113 91177308-0d34-0410-b5e6-96231b3b80d8
Be explicit with abs(). Visual Studio workaround.2011-03-05T10:29:25ZAndrew Trickatrick@apple.com2011-03-05T10:29:25Zurn:sha1:afc7d235e91a769f74d87bbe745558ed1b692ff7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127075 91177308-0d34-0410-b5e6-96231b3b80d8
Fix for -sched-high-latency-cycles in sched=list-ilp mode.2011-03-05T09:18:16ZAndrew Trickatrick@apple.com2011-03-05T09:18:16Zurn:sha1:5e84e3ccaa555bd48ecca384e93e55abd76fb40a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127071 91177308-0d34-0410-b5e6-96231b3b80d8
Missing comment.2011-03-05T08:04:11ZAndrew Trickatrick@apple.com2011-03-05T08:04:11Zurn:sha1:ab2e3e2d7074207e2a4bb15e2913fa83795bb1ca
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127068 91177308-0d34-0410-b5e6-96231b3b80d8
Increased the register pressure limit on x86_64 from 8 to 122011-03-05T08:00:22ZAndrew Trickatrick@apple.com2011-03-05T08:00:22Zurn:sha1:e0ef509aeb47b396cf1bdc170ca4f468f799719f
regs. This is the only change in this checkin that may affects the
default scheduler. With better register tracking and heuristics, it
doesn't make sense to artificially lower the register limit so much.
Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to
give the scheduler a way to account for div and sqrt on targets that
don't have an itinerary. It is currently defaults to 10 (the actual
number doesn't matter much), but only takes effect on non-default
schedulers: list-hybrid and list-ilp.
Added several heuristics that can be individually disabled for the
non-default sched=list-ilp mode. This helps us determine how much
better we can do on a given benchmark than the default
scheduler. Certain compute intensive loops run much faster in this
mode with the right set of heuristics, and it doesn't seem to have
much negative impact elsewhere. Not all of the heuristics are needed,
but we still need to experiment to decide which should be disabled by
default for sched=list-ilp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8