llvm/docs/CodeGenerator.html, branch release_31 http://llvm.org https://git.amat.us/llvm/atom/docs/CodeGenerator.html?h=release_31 2012-04-15T20:22:36Z Fix class name. 2012-04-15T20:22:36Z Jakub Staszak kubastaszak@gmail.com 2012-04-15T20:22:36Z urn:sha1:082d475fc95764fc1b7828a91c31fd4dddd9af8a git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154773 91177308-0d34-0410-b5e6-96231b3b80d8 Fix filename and register numbers. 2012-04-15T20:13:47Z Jakub Staszak kubastaszak@gmail.com 2012-04-15T20:13:47Z urn:sha1:00920f68a42251b5bde8537a78bd55f33615b441 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154771 91177308-0d34-0410-b5e6-96231b3b80d8 llvm/docs/*.html: Fix markups. 2012-03-27T11:25:16Z NAKAMURA Takumi geek4civic@gmail.com 2012-03-27T11:25:16Z urn:sha1:9c55f5965ba337469466fafec364b0ea6eca459f git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153508 91177308-0d34-0410-b5e6-96231b3b80d8 Add a new kind of MachineOperand: MO_RegisterMask. 2012-01-16T19:22:00Z Jakob Stoklund Olesen stoklund@2pi.dk 2012-01-16T19:22:00Z urn:sha1:7739cad69d2590f556afc9fc3048f967b5a3f4f6 Register masks will be used as a compact representation of large clobber lists. Currently, an x86 call instruction has some 40 operands representing call-clobbered registers. That's more than 1kB of useless operands per call site. A register mask operand references a bit mask of call-preserved registers, everything else is clobbered. The bit mask will typically come from TargetRegisterInfo::getCallPreservedMask(). By abandoning ImplicitDefs for call-clobbered registers, it also becomes possible to share call instruction descriptions between calling conventions, and we can get rid of the WINCALL* instructions. This patch introduces the new operand kind. Future patches will add RegMask support to target-independent passes before finally the fixed clobber lists can be removed from call instruction descriptions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148250 91177308-0d34-0410-b5e6-96231b3b80d8 Adding a Hexagon cell for segmented stacks, as they have been implemented for X86 and not Sparc... 2012-01-16T13:16:05Z Joe Abbey jabbey@arxan.com 2012-01-16T13:16:05Z urn:sha1:a0c1fc3bd308a0db86dc9a3ed587cc80be71fb3c Committed as obvious git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148237 91177308-0d34-0410-b5e6-96231b3b80d8 Add high level description of MachineInstr bundles. 2011-12-14T21:32:14Z Evan Cheng evan.cheng@apple.com 2011-12-14T21:32:14Z urn:sha1:2e9c7244b9f46e3396ea0a3475418eae814db742 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146589 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon backend support 2011-12-12T21:14:40Z Tony Linthicum tlinth@codeaurora.org 2011-12-12T21:14:40Z urn:sha1:b4b54153ad760c69a00a08531abef4ed434a5092 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146412 91177308-0d34-0410-b5e6-96231b3b80d8 Add documentation for machine-independent DFA packetizer 2011-12-06T23:12:42Z Anshuman Dasgupta adasgupt@codeaurora.org 2011-12-06T23:12:42Z urn:sha1:6805b56e7786f754756526e82e5a29bc77d97e9e git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145988 91177308-0d34-0410-b5e6-96231b3b80d8 grammar. 2011-11-29T19:38:09Z Rafael Espindola rafael.espindola@gmail.com 2011-11-29T19:38:09Z urn:sha1:dda8c6ff9eeccf375592d287a41dd18af738e282 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145423 91177308-0d34-0410-b5e6-96231b3b80d8 Fix spelling/grammar errors found by Duncan. 2011-11-28T17:06:58Z Rafael Espindola rafael.espindola@gmail.com 2011-11-28T17:06:58Z urn:sha1:30c5fa24996d5945687bef2acc3b2ac1ef00f334 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145250 91177308-0d34-0410-b5e6-96231b3b80d8