llvm/docs/CodeGenerator.html, branch masterhttp://llvm.orghttps://git.amat.us/llvm/atom/docs/CodeGenerator.html?h=master2012-08-02T08:49:53ZSphinxify the Code Generator document.2012-08-02T08:49:53ZBill Wendlingisanbard@gmail.com2012-08-02T08:49:53Zurn:sha1:31ce7bf6beeafaee40a4db2d2eac695976c79fc9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161164 91177308-0d34-0410-b5e6-96231b3b80d8
Remove/modify C backend references from LLVM documentation.2012-06-14T16:52:55ZDavid Blaikiedblaikie@gmail.com2012-06-14T16:52:55Zurn:sha1:722f2544b2bf3c686e13f43da31f283e77b1b0c6
Patch by Wei-Ren Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158456 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the old register list functions from MCRegisterInfo.2012-06-01T23:28:34ZJakob Stoklund Olesenstoklund@2pi.dk2012-06-01T23:28:34Zurn:sha1:22de91aec556d44ee580c2e42f45c7675da98349
These functions exposed the layout of the underlying data tables as
null-terminated uint16_t arrays.
Use the new MCSubRegIterator, MCSuperRegIterator, and MCRegAliasIterator
classes instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157855 91177308-0d34-0410-b5e6-96231b3b80d8
[docs] Update HTML pages to refer to CSS in a way that works locally and with Sphinx.2012-04-19T20:20:34ZDaniel Dunbardaniel@zuster.org2012-04-19T20:20:34Zurn:sha1:adea497673dab74b08fa2546e69619f1abe55662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155153 91177308-0d34-0410-b5e6-96231b3b80d8
Fix class name.2012-04-15T20:22:36ZJakub Staszakkubastaszak@gmail.com2012-04-15T20:22:36Zurn:sha1:082d475fc95764fc1b7828a91c31fd4dddd9af8a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154773 91177308-0d34-0410-b5e6-96231b3b80d8
Fix filename and register numbers.2012-04-15T20:13:47ZJakub Staszakkubastaszak@gmail.com2012-04-15T20:13:47Zurn:sha1:00920f68a42251b5bde8537a78bd55f33615b441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154771 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/docs/*.html: Fix markups.2012-03-27T11:25:16ZNAKAMURA Takumigeek4civic@gmail.com2012-03-27T11:25:16Zurn:sha1:9c55f5965ba337469466fafec364b0ea6eca459f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153508 91177308-0d34-0410-b5e6-96231b3b80d8
Add a new kind of MachineOperand: MO_RegisterMask.2012-01-16T19:22:00ZJakob Stoklund Olesenstoklund@2pi.dk2012-01-16T19:22:00Zurn:sha1:7739cad69d2590f556afc9fc3048f967b5a3f4f6
Register masks will be used as a compact representation of large clobber
lists. Currently, an x86 call instruction has some 40 operands
representing call-clobbered registers. That's more than 1kB of useless
operands per call site.
A register mask operand references a bit mask of call-preserved
registers, everything else is clobbered. The bit mask will typically
come from TargetRegisterInfo::getCallPreservedMask().
By abandoning ImplicitDefs for call-clobbered registers, it also becomes
possible to share call instruction descriptions between calling
conventions, and we can get rid of the WINCALL* instructions.
This patch introduces the new operand kind. Future patches will add
RegMask support to target-independent passes before finally the fixed
clobber lists can be removed from call instruction descriptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148250 91177308-0d34-0410-b5e6-96231b3b80d8
Adding a Hexagon cell for segmented stacks, as they have been implemented for X86 and not Sparc...2012-01-16T13:16:05ZJoe Abbeyjabbey@arxan.com2012-01-16T13:16:05Zurn:sha1:a0c1fc3bd308a0db86dc9a3ed587cc80be71fb3c
Committed as obvious
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148237 91177308-0d34-0410-b5e6-96231b3b80d8
Add high level description of MachineInstr bundles.2011-12-14T21:32:14ZEvan Chengevan.cheng@apple.com2011-12-14T21:32:14Zurn:sha1:2e9c7244b9f46e3396ea0a3475418eae814db742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146589 91177308-0d34-0410-b5e6-96231b3b80d8