llvm, branch testinghttp://llvm.orghttps://git.amat.us/llvm/atom/?h=testing2013-03-26T02:28:59ZUpdating branches/google/testing to r1777032013-03-26T02:28:59ZAlexander Kornienkoalexfh@google.com2013-03-26T02:28:59Zurn:sha1:d934545ae6a00aa8a8179a93d11cbd93a5240849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/google/testing@177985 91177308-0d34-0410-b5e6-96231b3b80d8
Reorder the DIFile field in DILexicalBlock to become a prefix common with other DIScopes2013-03-22T05:47:44ZDavid Blaikiedblaikie@gmail.com2013-03-22T05:47:44Zurn:sha1:c204410d6bc435e7cb8ea768759a54135e8e92b5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177703 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the empty directory. Silly git-svn.2013-03-22T05:42:33ZChandler Carruthchandlerc@gmail.com2013-03-22T05:42:33Zurn:sha1:4087d67a567c2e276354e3778463f97c6ee0c021
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177702 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the ARM-specific variant of this test. It's already covered by2013-03-22T05:16:46ZChandler Carruthchandlerc@gmail.com2013-03-22T05:16:46Zurn:sha1:d854299712e253b287a1bb7e890be1f78179ffb6
the ARM build bots, and it adds a weird case to the test suite where
a test uses as inputs files in the parent directory.
Talked about this with Dave on IRC and he's fine with this approach even
though it isn't optimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177700 91177308-0d34-0410-b5e6-96231b3b80d8
Introduce LLVM_STATIC_ASSERT macro, which expands to C/C++'s static_assert on compilers which support it.2013-03-22T03:10:51ZArgyrios Kyrtzidisakyrtzi@gmail.com2013-03-22T03:10:51Zurn:sha1:d1995b2a362c45d4d119b0cec8977360dd6ef33f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177699 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r177543: Add timing of the IR parsing code with a new2013-03-22T02:20:34ZChandler Carruthchandlerc@gmail.com2013-03-22T02:20:34Zurn:sha1:f0b0f1f9d97f4cf4d2f00c60fbc3d377a93465f8
-time-ir-parsing flag
This breaks the layering of the Support library. We can't add an
implementation side to IRReader because it refers directly to entities
only accessible as part of the IR, AsmParser, and BitcodeReader
libraries. It can only be used in a context where all of those libraries
will be available.
We'll need to find some other way to get this functionality, and
hopefully solve the long-standing layering problem of IRReader.h...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177695 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the invalid opcode for Mips branch instructions in the assembler2013-03-22T00:29:10ZJack Carterjack.carter@imgtec.com2013-03-22T00:29:10Zurn:sha1:d3107fbc54a5b5156f0aabc8788724f1469eb9df
For mips a branch an 18-bit signed offset (the 16-bit
offset field shifted left 2 bits) is added to the
address of the instruction following the branch
(not the branch itself), in the branch delay slot,
to form a PC-relative effective target address.
Previously, the code generator did not perform the
shift of the immediate branch offset which resulted
in wrong instruction opcode. This patch fixes the issue.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
This patch that enables the Mips assembler to use symbols for offset for instructions2013-03-22T00:05:30ZJack Carterjack.carter@imgtec.com2013-03-22T00:05:30Zurn:sha1:25df6a93f3324bd30f44dcb95fd17aff0a92d438
This patch uses the generated instruction info tables to
identify memory/load store instructions.
After successful matching and based on the operand type
and size, it generates additional instructions to the output.
Contributor: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class2013-03-21T23:45:03ZHal Finkelhfinkel@anl.gov2013-03-21T23:45:03Zurn:sha1:7697370adff8983e2a3de493362f0d8c9f9b0e17
As Jakob pointed out in his review of r177423, having a shared ZERO
register between the 32- and 64-bit register classes causes this
odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended,
this adds a ZERO8 register which differentiates the 32- and 64-bit
zeros.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
Add TableGen ctags(1) emitter and helper script.2013-03-21T23:40:38ZSean Silvasilvas@purdue.edu2013-03-21T23:40:38Zurn:sha1:426db657da8753921f21c676b91c527e1b77878c
To use this in conjunction with exuberant ctags to generate a single
combined tags file, run tblgen first and then
$ ctags --append [...]
Since some identifiers have corresponding definitions in C++ code,
it can be useful (if using vim) to also use cscope, and
:set cscopetagorder=1
so that
:tag X
will preferentially select the tablegen symbol, while
:cscope find g X
will always find the C++ symbol.
Patch by Kevin Schoedel!
(a couple small formatting changes courtesy of clang-format)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177682 91177308-0d34-0410-b5e6-96231b3b80d8