/*
* wm8961.c -- WM8961 ALSA SoC Audio driver
*
* Author: Mark Brown
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Currently unimplemented features:
* - ALC
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "wm8961.h"
#define WM8961_MAX_REGISTER 0xFC
static u16 wm8961_reg_defaults[] = {
0x009F, /* R0 - Left Input volume */
0x009F, /* R1 - Right Input volume */
0x0000, /* R2 - LOUT1 volume */
0x0000, /* R3 - ROUT1 volume */
0x0020, /* R4 - Clocking1 */
0x0008, /* R5 - ADC & DAC Control 1 */
0x0000, /* R6 - ADC & DAC Control 2 */
0x000A, /* R7 - Audio Interface 0 */
0x01F4, /* R8 - Clocking2 */
0x0000, /* R9 - Audio Interface 1 */
0x00FF, /* R10 - Left DAC volume */
0x00FF, /* R11 - Right DAC volume */
0x0000, /* R12 */
0x0000, /* R13 */
0x0040, /* R14 - Audio Interface 2 */
0x0000, /* R15 - Software Reset */
0x0000, /* R16 */
0x007B, /* R17 - ALC1 */
0x0000, /* R18 - ALC2 */
0x0032, /* R19 - ALC3 */
0x0000, /* R20 - Noise Gate */
0x00C0, /* R21 - Left ADC volume */
0x00C0, /* R22 - Right ADC volume */
0x0120, /* R23 - Additional control(1) */
0x0000, /* R24 - Additional control(2) */
0x0000, /* R25 - Pwr Mgmt (1) */
0x0000, /* R26 - Pwr Mgmt (2) */
0x0000, /* R27 - Additional Control (3) */
0x0000, /* R28 - Anti-pop */
0x0000, /* R29 */
0x005F, /* R30 - Clocking 3 */
0x0000, /* R31 */
0x0000, /* R32 - ADCL signal path */
0x0000, /* R33 - ADCR signal path */
0x0000, /* R34 */
0x0000, /* R35 */
0x0000, /* R36 */
0x0000, /* R37 */
0x0000, /* R38 */
0x0000, /* R39 */
0x0000, /* R40 - LOUT2 volume */
0x0000, /* R41 - ROUT2 volume */
0x0000, /* R42 */
0x0000, /* R43 */
0x0000, /* R44 */
0x0000, /* R45 */
0x0000, /* R46 */
0x0000, /* R47 - Pwr Mgmt (3) */
0x0023, /* R48 - Additional Control (4) */
0x0000, /* R49 - Class D Control 1 */
0x0000, /* R50 */
0x0003, /* R51 - Class D Control 2 */
0x0000, /* R52 */
0x0000, /* R53 */
0x0000, /* R54 */
0x0000, /* R55 */
0x0106, /* R56 - Clocking 4 */
0x0000, /* R57 - DSP Sidetone 0 */
0x0000, /* R58 - DSP Sidetone 1 */
0x0000, /* R59 */
0x0000, /* R60 - DC Servo 0 */
0x0000, /* R61 - DC Servo 1 */
0x0000, /* R62 */
0x015E, /* R63 - DC Servo 3 */
0x0010, /* R64 */
0x0010, /* R65 - DC Servo 5 */
0x0000, /* R66 */
0x0001, /* R67 */
0x0003, /* R68 - Analogue PGA Bias */
0x0000, /* R69 - Analogue HP 0 */
0x0060, /* R70 */
0x01FB, /* R71 - Analogue HP 2 */
0x0000, /* R72 - Charge Pump 1 */
0x0065, /* R73 */
0x005F, /* R74 */
0x0059, /* R75 */
0x006B, /* R76 */
0x0038, /* R77 */
0x000C, /* R78 */
0x000A, /* R79 */
0x006B, /* R80 */
0x0000, /* R81 */
0x0000, /* R82 - Charge Pump B */
0x0087, /* R83 */
0x0000, /* R84 */
0x005C, /* R85 */
0x0000, /* R86 */
0x0000, /* R87 - Write Sequencer 1 */
0x0000, /* R88 - Write Sequencer 2 */
0x0000, /* R89 - Write Sequencer 3 */
0x0000, /* R90 - Write Sequencer 4 */
0x0000, /* R91 - Write Sequencer 5 */
0x0000, /* R92 - Write Sequencer 6 */
0x0000, /* R93 - Write Sequencer 7 */
0x0000, /* R94 */
0x0000, /* R95 */
0x0000, /* R96 */
0x0000, /* R97 */
0x0000, /* R98 */
0x0000, /* R99 */