/*
* cs42l52.c -- CS42L52 ALSA SoC audio driver
*
* Copyright 2012 CirrusLogic, Inc.
*
* Author: Georgi Vlaev <joe@nucleusys.com>
* Author: Brian Austin <brian.austin@cirrus.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/cs42l52.h>
#include "cs42l52.h"
struct sp_config {
u8 spc, format, spfs;
u32 srate;
};
struct cs42l52_private {
struct regmap *regmap;
struct snd_soc_codec *codec;
struct device *dev;
struct sp_config config;
struct cs42l52_platform_data pdata;
u32 sysclk;
u8 mclksel;
u32 mclk;
u8 flags;
#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
struct input_dev *beep;
struct work_struct beep_work;
int beep_rate;
#endif
};
static const struct reg_default cs42l52_reg_defaults[] = {
{ CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
{ CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
{ CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
{ CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
{ CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
{ CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
{ CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
{ CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
{ CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
{ CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
{ CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
{ CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
{ CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
{ CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
{ CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
{ CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
{ CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
{ CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
{ CS42L52_PASSTHRUB_VOL, 0x00 <