path: root/include/asm-ppc/mv64x60_defs.h

/*
 * include/asm-ppc/gt64260_defs.h
 *
 * Register definitions for the Marvell/Galileo GT64260, MV64360, etc.
 * host bridges.
 *
 * Author: Mark A. Greer <mgreer@mvista.com>
 *
 * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#ifndef __ASMPPC_MV64x60_DEFS_H
#define __ASMPPC_MV64x60_DEFS_H

/*
 * Define the Marvell bridges that are supported
 */
#define	MV64x60_TYPE_INVALID			0
#define	MV64x60_TYPE_GT64260A			1
#define	MV64x60_TYPE_GT64260B			2
#define	MV64x60_TYPE_MV64360			3
#define	MV64x60_TYPE_MV64361			4
#define	MV64x60_TYPE_MV64362			5
#define	MV64x60_TYPE_MV64460			6


/* Revisions of each supported chip */
#define	GT64260_REV_A				0x10
#define	GT64260_REV_B				0x20
#define	MV64360					0x01
#define	MV64460					0x01

/* Minimum window size supported by 64260 is 1MB */
#define GT64260_WINDOW_SIZE_MIN			0x00100000
#define MV64360_WINDOW_SIZE_MIN			0x00010000

#define	MV64x60_TCLK_FREQ_MAX			133333333U

/* IRQ's for embedded controllers */
#define	MV64x60_IRQ_DEV				1
#define	MV64x60_IRQ_CPU_ERR			3
#define	MV64x60_IRQ_TIMER_0_1			8
#define	MV64x60_IRQ_TIMER_2_3			9
#define	MV64x60_IRQ_TIMER_4_5			10
#define	MV64x60_IRQ_TIMER_6_7			11
#define	MV64x60_IRQ_P1_GPP_0_7			24
#define	MV64x60_IRQ_P1_GPP_8_15			25
#define	MV64x60_IRQ_P1_GPP_16_23		26
#define	MV64x60_IRQ_P1_GPP_24_31		27
#define	MV64x60_IRQ_DOORBELL			28
#define	MV64x60_IRQ_ETH_0			32
#define	MV64x60_IRQ_ETH_1			33
#define	MV64x60_IRQ_ETH_2			34
#define	MV64x60_IRQ_SDMA_0			36
#define	MV64x60_IRQ_I2C				37
#define	MV64x60_IRQ_BRG				39
#define	MV64x60_IRQ_MPSC_0			40
#define	MV64x60_IRQ_MPSC_1			42
#define	MV64x60_IRQ_COMM			43
#define	MV64x60_IRQ_P0_GPP_0_7			56
#define	MV64x60_IRQ_P0_GPP_8_15			57
#define	MV64x60_IRQ_P0_GPP_16_23		58
#define	MV64x60_IRQ_P0_GPP_24_31		59

#define	MV64360_IRQ_PCI0			12
#define	MV64360_IRQ_SRAM_PAR_ERR		13
#define	MV64360_IRQ_PCI1			16
#define	MV64360_IRQ_SDMA_1			38

#define	MV64x60_IRQ_GPP0			64
#define	MV64x60_IRQ_GPP1			65
#define	MV64x60_IRQ_GPP2			66
#define	MV64x60_IRQ_GPP3			67
#define	MV64x60_IRQ_GPP4			68
#define	MV64x60_IRQ_GPP5			69
#define	MV64x60_IRQ_GPP6			70
#define	MV64x60_IRQ_GPP7			71
#define	MV64x60_IRQ_GPP8			72
#define	MV64x60_IRQ_GPP9			73
#define	MV64x60_IRQ_GPP10			74
#define	MV64x60_IRQ_GPP11			75
#define	MV64x60_IRQ_GPP12			76
#define	MV64x60_IRQ_GPP13			77
#define	MV64x60_IRQ_GPP14			78
#define	MV64x60_IRQ_GPP15			79
#define	MV64x60_IRQ_GPP16			80
#define	MV64x60_IRQ_GPP17			81
#define	MV64x60_IRQ_GPP18			82
#define	MV64x60_IRQ_GPP19			83
#define	MV64x60_IRQ_GPP20			84
#define	MV64x60_IRQ_GPP21			85
#define	MV64x60_IRQ_GPP22			86
#define	MV64x60_IRQ_GPP23			87
#define	MV64x60_IRQ_GPP24			88
#define	MV64x60_IRQ_GPP25			89
#define	MV64x60_IRQ_GPP26			90
#define	MV64x60_IRQ_GPP27			91
#define	MV64x60_IRQ_GPP28			92
#define	MV64x60_IRQ_GPP29			93
#define	MV64x60_IRQ_GPP30			94
#define	MV64x60_IRQ_GPP31			95

/* Offsets for register blocks */
#define	GT64260_ENET_PHY_ADDR			0x2000
#define	GT64260_ENET_ESMIR			0x2010
#define GT64260_ENET_0_OFFSET			0x2400
#define GT64260_ENET_1_OFFSET			0x2800
#define GT64260_ENET_2_OFFSET			0x2c00
#define	MV64x60_SDMA_0_OFFSET			0x4000
#define	MV64x60_SDMA_1_OFFSET			0x6000
#define	MV64x60_MPSC_0_OFFSET			0x8000
#define	MV64x60_MPSC_1_OFFSET			0x9000
#define	MV64x60_MPSC_ROUTING_OFFSET		0xb400
#define	MV64x60_SDMA_INTR_OFFSET		0xb800
#define	MV64x60_BRG_0_OFFSET			0xb200
#define	MV64x60_BRG_1_OFFSET			0xb208

/*
 *****************************************************************************
 *
 *	CPU Interface Registers
 *
 *****************************************************************************
 */

/* CPU physical address of bridge's registers */
#define MV64x60_INTERNAL_SPACE_DECODE		0x0068
#define MV64x60_INTERNAL_SPACE_SIZE		0x10000
#define MV64x60_INTERNAL_SPACE_DEFAULT_ADDR	0x14000000

#define	MV64360_CPU_BAR_ENABLE			0x0278

/* CPU Memory Controller Window Registers (4 windows) */
#define	MV64x60_CPU2MEM_WINDOWS			4

#define	MV64x60_CPU2MEM_0_BASE			0x0008
#define	MV64x60_CPU2MEM_0_SIZE			0x0010
#define	MV64x60_CPU2MEM_1_BASE			0x0208
#define	MV64x60_CPU2MEM_1_SIZE			0x0210
#define	MV64x60_CPU2MEM_2_BASE			0x0018
#define	MV64x60_CPU2MEM_2_SIZE			0x0020
#define	MV64x60_CPU2MEM_3_BASE			0x0218
#define	MV64x60_CPU2MEM_3_SIZE			0x0220

/* CPU Device Controller Window Registers (4 windows) */
#define	MV64x60_CPU2DEV_WINDOWS			4

#define	MV64x60_CPU2DEV_0_BASE			0x0028
#define	MV64x60_CPU2DEV_0_SIZE			0x0030
#define	MV64x60_CPU2DEV_1_BASE			0x0228
#define	MV64x60_CPU2DEV_1_SIZE			0x0230
#define	MV64x60_CPU2DEV_2_BASE			0x0248
#define	MV64x60_CPU2DEV_2_SIZE			0x0250
#define	MV64x60_CPU2DEV_3_BASE			0x0038
#define	MV64x60_CPU2DEV_3_SIZE			0x0040

#define	MV64x60_CPU2BOOT_0_BASE			0x0238
#define	MV64x60_CPU2BOOT_0_SIZE			0x0240

#define	MV64360_CPU2SRAM_BASE			0x0268

/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
#define	MV64x60_PCI_BUSES			2
#define	MV64x60_PCI_IO_WINDOWS_PER_BUS		1
#define	MV64x60_PCI_MEM_WINDOWS_PER_BUS		4

#define	MV64x60_CPU2PCI_SWAP_BYTE		0x00000000
#define	MV64x60_CPU2PCI_SWAP_NONE		0x01000000
#define	MV64x60_CPU2PCI_SWAP_BYTE_WORD		0x02000000
#define	MV64x60_CPU2PCI_SWAP_WORD		0x03000000

#define	MV64x60_CPU2PCI_MEM_REQ64		(1<<27)

#define	MV64x60_CPU2PCI0_IO_BASE		0x0048
#define	MV64x60_CPU2PCI0_IO_SIZE		0x0050
#define	MV64x60_CPU2PCI0_MEM_0_BASE		0x0058
#define	MV64x60_CPU2PCI0_MEM_0_SIZE		0x0060
#define	MV64x60_CPU2PCI0_MEM_1_BASE		0x0080
#define	MV64x60_CPU2PCI0_MEM_1_SIZE		0x0088
#define	MV64x60_CPU2PCI0_MEM_2_BASE		0x0258
#define	MV64x60_CPU2PCI0_MEM_2_SIZE		0x0260
#define	MV64x60_CPU2PCI0_MEM_3_BASE		0x0280
#define	MV64x60_CPU2PCI0_MEM_3_SIZE		0x0288

#define	MV64x60_CPU2PCI0_IO_REMAP		0x00f0
#define	MV64x60_CPU2PCI0_MEM_0_REMAP_LO		0x00f8
#define	MV64x60_CPU2PCI0_MEM_0_REMAP_HI		0x0320
#define	MV64x60_CPU2PCI0_MEM_1_REMAP_LO		0x0100
#define	MV64x60_CPU2PCI0_MEM_1_REMAP_HI		0x0328
#define	MV64x60_CPU2PCI0_MEM_2_REMAP_LO		0x02f8
#define	MV64x60_CPU2PCI0_MEM_2_REMAP_HI		0x0330
#define	MV64x60_CPU2PCI0_MEM_3_REMAP_LO		0x0300
#define	MV64x60_CPU2PCI0_MEM_3_REMAP_HI		0x0338

#define	MV64x60_CPU2PCI1_IO_BASE		0x0090
#define	MV64x60_CPU2PCI1_IO_SIZE		0x0098
#define	MV64x60_CPU2PCI1_MEM_0_BASE		0x00a0
#define	MV64x60_CPU2PCI1_MEM_0_SIZE		0x00a8
#define	MV64x60_CPU2PCI1_MEM_1_BASE		0x00b0
#define	MV64x60_CPU2PCI1_MEM_1_SIZE		0x00b8
#define	MV64x60_CPU2PCI1_MEM_2_BASE		0x02a0
#define	MV64x60_CPU2PCI1_MEM_2_SIZE		0x02a8
#define	MV64x60_CPU2PCI1_MEM_3_BASE		0x02b0
#define	MV64x60_CPU2PCI1_MEM_3_SIZE		0x02b8

#define	MV64x60_CPU2PCI1_IO_REMAP		0x0108
#define	MV64x60_CPU2PCI1_MEM_0_REMAP_LO		0x0110
#define	MV64x60_CPU2PCI1_MEM_0_REMAP_HI		0x0340
#define	MV64x60_CPU2PCI1_MEM_1_REMAP_LO		0x0118
#define	MV64x60_CPU2PCI1_MEM_1_REMAP_HI		0x0348
#define	MV64x60_CPU2PCI1_MEM_2_REMAP_LO		0x0310
#define	MV64x60_CPU2PCI1_MEM_2_REMAP_HI		0x0350
#define	MV64x60_CPU2PCI1_MEM_3_REMAP_LO		0x0318
#define	MV64x60_CPU2PCI1_MEM_3_REMAP_HI		0x0358

/* CPU Control Registers */
#define MV64x60_CPU_CONFIG			0x0000
#define MV64x60_CPU_MODE			0x0120
#define MV64x60_CPU_MASTER_CNTL			0x0160
#define MV64x60_CPU_XBAR_CNTL_LO		0x0150
#define MV64x60_CPU_XBAR_CNTL_HI		0x0158
#define MV64x60_CPU_XBAR_TO			0x0168

#define GT64260_CPU_RR_XBAR_CNTL_LO		0x0170
#define GT64260_CPU_RR_XBAR_CNTL_HI		0x0178

#define MV64360_CPU_PADS_CALIBRATION		0x03b4
#define MV64360_CPU_RESET_SAMPLE_LO		0x03c4
#define MV64360_CPU_RESET_SAMPLE_HI		0x03d4

/* SMP Register Map */
#define MV64360_WHO_AM_I			0x0200
#define MV64360_CPU0_DOORBELL			0x0214
#define MV64360_CPU0_DOORBELL_CLR		0x021c
#define MV64360_CPU0_DOORBELL_MASK		0x0234
#define MV64360_CPU1_DOORBELL			0x0224
#define MV64360_CPU1_DOORBELL_CLR		0x022c
#define MV64360_CPU1_DOORBELL_MASK		0x023c
#define MV64360_CPUx_DOORBELL(x)		(0x0214 + ((x)*0x10))
#define MV64360_CPUx_DOORBELL_CLR(x)		(0x021c + ((x)*0x10))
#define MV64360_CPUx_DOORBELL_MASK(x)		(0x0234 + ((x)*0x08))
#define MV64360_SEMAPHORE_0			0x0244
#define MV64360_SEMAPHORE_1			0x024c
#define MV64360_SEMAPHORE_2			0x0254
#define MV64360_SEMAPHORE_3			0x025c
#define MV64360_SEMAPHORE_4			0x0264
#define MV64360_SEMAPHORE_5			0x026c
#define MV64360_SEMAPHORE_6			0x0274
#define MV64360_SEMAPHORE_7			0x027c

/* CPU Sync Barrier Registers */
#define GT64260_CPU_SYNC_BARRIER_PCI0		0x00c0
#define GT64260_CPU_SYNC_BARRIER_PCI1		0x00c8

#define MV64360_CPU0_SYNC_BARRIER_TRIG		0x00c0
#define MV64360_CPU0_SYNC_BARRIER_VIRT		0x00c8
#define MV64360_CPU1_SYNC_BARRIER_TRIG		0x00d0
#define MV64360_CPU1_SYNC_BARRIER_VIRT		0x00d8

/* CPU Deadlock and Ordering registers (Rev B part only) */
#define GT64260_CPU_DEADLOCK_ORDERING			0x02d0
#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH		0x02d8
#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE	0x02e0

/* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
#define	MV64x260_CPU_PROT_WINDOWS		4

#define	GT64260_CPU_PROT_ACCPROTECT		(1<<16)
#define	GT64260_CPU_PROT_WRPROTECT		(1<<17)
#define	GT64260_CPU_PROT_CACHEPROTECT		(1<<18)

#define	MV64360_CPU_PROT_ACCPROTECT		(1<<20)
#define	MV64360_CPU_PROT_WRPROTECT		(1<<21)
#define	MV64360_CPU_PROT_CACHEPROTECT		(1<<22)
#define	MV64360_CPU_PROT_WIN_ENABLE		(1<<31)

#define MV64x60_CPU_PROT_BASE_0			0x0180
#define MV64x60_CPU_PROT_SIZE_0			0x0188
#define MV64x60_CPU_PROT_BASE_1			0x0190
#define MV64x60_CPU_PROT_SIZE_1			0x0198
#define MV64x60_CPU_PROT_BASE_2			0x01a0
#define MV64x60_CPU_PROT_SIZE_2			0x01a8
#define MV64x60_CPU_PROT_BASE_3			0x01b0
#define MV64x60_CPU_PROT_SIZE_3			0x01b8

#define GT64260_CPU_PROT_BASE_4			0x01c0
#define GT64260_CPU_PROT_SIZE_4			0x01c8
#define GT64260_CPU_PROT_BASE_5			0x01d0
#define GT64260_CPU_PROT_SIZE_5			0x01d8
#define GT64260_CPU_PROT_BASE_6			0x01e0
#define GT64260_CPU_PROT_SIZE_6			0x01e8
#define GT64260_CPU_PROT_BASE_7			0x01f0
#define GT64260_CPU_PROT_SIZE_7			0x01f8

/* CPU Snoop Control Registers (64260 only) */
#define	GT64260_CPU_SNOOP_WINDOWS		4

#define	GT64260_CPU_SNOOP_NONE			0x00000000
#define	GT64260_CPU_SNOOP_WT			0x00010000
#define	GT64260_CPU_SNOOP_WB			0x00020000
#define	GT64260_CPU_SNOOP_MASK			0x00030000
#define	GT64260_CPU_SNOOP_ALL_BITS		GT64260_CPU_SNOOP_MASK

#define GT64260_CPU_SNOOP_BASE_0		0x0380
#define GT64260_CPU_SNOOP_SIZE_0		0x0388
#define GT64260_CPU_SNOOP_BASE_1		0x0390
#define GT64260_CPU_SNOOP_SIZE_1		0x0398
#define GT64260_CPU_SNOOP_BASE_2		0x03a0
#define GT64260_CPU_SNOOP_SIZE_2		0x03a8
#define GT64260_CPU_SNOOP_BASE_3		0x03b0
#define GT64260_CPU_SNOOP_SIZE_3		0x03b8

/* CPU Snoop Control Registers (64360 only) */
#define	MV64360_CPU_SNOOP_WINDOWS		4
#define	MV64360_CPU_SNOOP_NONE			0x00000000
#define	MV64360_CPU_SNOOP_WT			0x00010000
#define	MV64360_CPU_SNOOP_WB			0x00020000
#define	MV64360_CPU_SNOOP_MASK			0x00030000
#define	MV64360_CPU_SNOOP_ALL_BITS		MV64360_CPU_SNOOP_MASK


/* CPU Error Report Registers */
#define MV64x60_CPU_ERR_ADDR_LO			0x0070
#define MV64x60_CPU_ERR_ADDR_HI			0x0078
#define MV64x60_CPU_ERR_DATA_LO			0x0128
#define MV64x60_CPU_ERR_DATA_HI			0x0130
#define MV64x60_CPU_ERR_PARITY			0x0138
#define MV64x60_CPU_ERR_CAUSE			0x0140
#define MV64x60_CPU_ERR_MASK			0x0148

/*
 *****************************************************************************
 *
 *	SRAM Controller Registers
 *
 *****************************************************************************
 */

#define	MV64360_SRAM_CONFIG			0x0380
#define	MV64360_SRAM_TEST_MODE			0x03f4
#define	MV64360_SRAM_ERR_CAUSE			0x0388
#define	MV64360_SRAM_ERR_ADDR_LO		0x0390
#define	MV64360_SRAM_ERR_ADDR_HI		0x03f8
#define	MV64360_SRAM_ERR_DATA_LO		0x0398
#define	MV64360_SRAM_ERR_DATA_HI		0x03a0
#define	MV64360_SRAM_ERR_PARITY			0x03a8

#define	MV64360_SRAM_SIZE			0x00040000 /* 2Mb/256KB SRAM */

/*
 *****************************************************************************
 *
 *	SDRAM/MEM Controller Registers
 *
 *****************************************************************************
 */

/* SDRAM Config Registers (64260) */
#define	GT64260_SDRAM_CONFIG			0x0448

/* SDRAM Error Report Registers (64260) */
#define	GT64260_SDRAM_ERR_DATA_LO		0x0484
#define	GT64260_SDRAM_ERR_DATA_HI		0x0480
#define	GT64260_SDRAM_ERR_ADDR			0x0490
#define	GT64260_SDRAM_ERR_ECC_RCVD		0x0488
#define	GT64260_SDRAM_ERR_ECC_CALC		0x048c
#define	GT64260_SDRAM_ERR_ECC_CNTL		0x0494
#define	GT64260_SDRAM_ERR_ECC_ERR_CNT		0x0498

/* SDRAM Config Registers (64360) */
#define	MV64360_SDRAM_CONFIG			0x1400

/* SDRAM Control Registers */
#define MV64360_D_UNIT_CONTROL_LOW		0x1404
#define MV64360_D_UNIT_CONTROL_HIGH		0x1424
#define MV64460_D_UNIT_MMASK			0x14b0

/* SDRAM Error Report Registers (64360) */
#define	MV64360_SDRAM_ERR_DATA_LO		0x1444
#define	MV64360_SDRAM_ERR_DATA_HI		0x1440
#define	MV64360_SDRAM_ERR_ADDR			0x1450
#define	MV64360_SDRAM_ERR_ECC_RCVD		0x1448
#define	MV64360_SDRAM_ERR_ECC_CALC		0x144c
#define	MV64360_SDRAM_ERR_ECC_CNTL		0x1454
#define	MV64360_SDRAM_ERR_ECC_ERR_CNT		0x1458

/*
 *****************************************************************************
 *
 *	Device/BOOT Controller Registers
 *
 *****************************************************************************
 */

/* Device Control Registers */
#define	MV64x60_DEV_BANK_PARAMS_0		0x045c
#define	MV64x60_DEV_BANK_PARAMS_1		0x0460
#define	MV64x60_DEV_BANK_PARAMS_2		0x0464
#define	MV64x60_DEV_BANK_PARAMS_3		0x0468
#define	MV64x60_DEV_BOOT_PARAMS			0x046c
#define	MV64x60_DEV_IF_CNTL			0x04c0
#define	MV64x60_DEV_IF_XBAR_CNTL_LO		0x04c8
#define	MV64x60_DEV_IF_XBAR_CNTL_HI		0x04cc
#define	MV64x60_DEV_IF_XBAR_CNTL_TO		0x04c4

/* Device Interrupt Registers */
#define	MV64x60_DEV_INTR_CAUSE			0x04d0
#define	MV64x60_DEV_INTR_MASK			0x04d4
#define	MV64x60_DEV_INTR_ERR_ADDR		0x04d8

#define	MV64360_DEV_INTR_ERR_DATA		0x04dc
#define	MV64360_DEV_INTR_ERR_PAR		0x04e0

/*
 *****************************************************************************
 *
 *	PCI Bridge Interface Registers
 *
 *****************************************************************************
 */

/* PCI Configuration Access Registers */
#define	MV64x60_PCI0_CONFIG_ADDR		0x0cf8
#define	MV64x60_PCI0_CONFIG_DATA		0x0cfc
#define	MV64x60_PCI0_IACK			0x0c34

#define	MV64x60_PCI1_CONFIG_ADDR		0x0c78
#define	MV64x60_PCI1_CONFIG_DATA		0x0c7c
#define	MV64x60_PCI1_IACK			0x0cb4

/* PCI Control Registers */
#define	MV64x60_PCI0_CMD			0x0c00
#define	MV64x60_PCI0_MODE			0x0d00
#define	MV64x60_PCI0_TO_RETRY			0x0c04
#define	MV64x60_PCI0_RD_BUF_DISCARD_TIMER	0x0d04
#define	MV64x60_PCI0_MSI_TRIGGER_TIMER		0x0c38
#define	MV64x60_PCI0_ARBITER_CNTL		0x1d00
#define	MV64x60_PCI0_XBAR_CNTL_LO		0x1d08
<