path: root/include/asm-ppc/gt64260_defs.h

/*
 * include/asm-ppc/gt64260_defs.h
 *
 * Register definitions for the Marvell/Galileo GT64260 host bridge.
 *
 * Author: Mark A. Greer <mgreer@mvista.com>
 *
 * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#ifndef __ASMPPC_GT64260_DEFS_H
#define __ASMPPC_GT64260_DEFS_H

/*
 * Define a macro to represent the supported version of the 64260.
 */
#define	GT64260			0x01
#define	GT64260A		0x10

/*
 *****************************************************************************
 *
 *	CPU Interface Registers
 *
 *****************************************************************************
 */

/* CPU physical address of 64260's registers */
#define GT64260_INTERNAL_SPACE_DECODE			0x0068
#define GT64260_INTERNAL_SPACE_SIZE			0x10000
#define GT64260_INTERNAL_SPACE_DEFAULT_ADDR		0x14000000

/* CPU Memory Controller Window Registers (4 windows) */
#define	GT64260_CPU_SCS_DECODE_WINDOWS			4

#define	GT64260_CPU_SCS_DECODE_0_BOT			0x0008
#define	GT64260_CPU_SCS_DECODE_0_TOP			0x0010
#define	GT64260_CPU_SCS_DECODE_1_BOT			0x0208
#define	GT64260_CPU_SCS_DECODE_1_TOP			0x0210
#define	GT64260_CPU_SCS_DECODE_2_BOT			0x0018
#define	GT64260_CPU_SCS_DECODE_2_TOP			0x0020
#define	GT64260_CPU_SCS_DECODE_3_BOT			0x0218
#define	GT64260_CPU_SCS_DECODE_3_TOP			0x0220

/* CPU Device Controller Window Registers (4 windows) */
#define	GT64260_CPU_CS_DECODE_WINDOWS			4

#define	GT64260_CPU_CS_DECODE_0_BOT			0x0028
#define	GT64260_CPU_CS_DECODE_0_TOP			0x0030
#define	GT64260_CPU_CS_DECODE_1_BOT			0x0228
#define	GT64260_CPU_CS_DECODE_1_TOP			0x0230
#define	GT64260_CPU_CS_DECODE_2_BOT			0x0248
#define	GT64260_CPU_CS_DECODE_2_TOP			0x0250
#define	GT64260_CPU_CS_DECODE_3_BOT			0x0038
#define	GT64260_CPU_CS_DECODE_3_TOP			0x0040

#define	GT64260_CPU_BOOT_CS_DECODE_0_BOT		0x0238
#define	GT64260_CPU_BOOT_CS_DECODE_0_TOP		0x0240

/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
#define	GT64260_PCI_BUSES				2
#define	GT64260_PCI_IO_WINDOWS_PER_BUS			1
#define	GT64260_PCI_MEM_WINDOWS_PER_BUS			4

#define	GT64260_CPU_PCI_SWAP_BYTE			0x00000000
#define	GT64260_CPU_PCI_SWAP_NONE			0x01000000
#define	GT64260_CPU_PCI_SWAP_BYTE_WORD			0x02000000
#define	GT64260_CPU_PCI_SWAP_WORD			0x03000000
#define	GT64260_CPU_PCI_SWAP_MASK			0x07000000

#define	GT64260_CPU_PCI_MEM_REQ64			(1<<27)

#define	GT64260_CPU_PCI_0_IO_DECODE_BOT			0x0048
#define	GT64260_CPU_PCI_0_IO_DECODE_TOP			0x0050
#define	GT64260_CPU_PCI_0_MEM_0_DECODE_BOT		0x0058
#define	GT64260_CPU_PCI_0_MEM_0_DECODE_TOP		0x0060
#define	GT64260_CPU_PCI_0_MEM_1_DECODE_BOT		0x0080
#define	GT64260_CPU_PCI_0_MEM_1_DECODE_TOP		0x0088
#define	GT64260_CPU_PCI_0_MEM_2_DECODE_BOT		0x0258
#define	GT64260_CPU_PCI_0_MEM_2_DECODE_TOP		0x0260
#define	GT64260_CPU_PCI_0_MEM_3_DECODE_BOT		0x0280
#define	GT64260_CPU_PCI_0_MEM_3_DECODE_TOP		0x0288

#define	GT64260_CPU_PCI_0_IO_REMAP			0x00f0
#define	GT64260_CPU_PCI_0_MEM_0_REMAP_LO		0x00f8
#define	GT64260_CPU_PCI_0_MEM_0_REMAP_HI		0x0320
#define	GT64260_CPU_PCI_0_MEM_1_REMAP_LO		0x0100
#define	GT64260_CPU_PCI_0_MEM_1_REMAP_HI		0x0328
#define	GT64260_CPU_PCI_0_MEM_2_REMAP_LO		0x02f8
#define	GT64260_CPU_PCI_0_MEM_2_REMAP_HI		0x0330
#define	GT64260_CPU_PCI_0_MEM_3_REMAP_LO		0x0300
#define	GT64260_CPU_PCI_0_MEM_3_REMAP_HI		0x0338

#define	GT64260_CPU_PCI_1_IO_DECODE_BOT			0x0090
#define	GT64260_CPU_PCI_1_IO_DECODE_TOP			0x0098
#define	GT64260_CPU_PCI_1_MEM_0_DECODE_BOT		0x00a0
#define	GT64260_CPU_PCI_1_MEM_0_DECODE_TOP		0x00a8
#define	GT64260_CPU_PCI_1_MEM_1_DECODE_BOT		0x00b0
#define	GT64260_CPU_PCI_1_MEM_1_DECODE_TOP		0x00b8
#define	GT64260_CPU_PCI_1_MEM_2_DECODE_BOT		0x02a0
#define	GT64260_CPU_PCI_1_MEM_2_DECODE_TOP		0x02a8
#define	GT64260_CPU_PCI_1_MEM_3_DECODE_BOT		0x02b0
#define	GT64260_CPU_PCI_1_MEM_3_DECODE_TOP		0x02b8

#define	GT64260_CPU_PCI_1_IO_REMAP			0x0108
#define	GT64260_CPU_PCI_1_MEM_0_REMAP_LO		0x0110
#define	GT64260_CPU_PCI_1_MEM_0_REMAP_HI		0x0340
#define	GT64260_CPU_PCI_1_MEM_1_REMAP_LO		0x0118
#define	GT64260_CPU_PCI_1_MEM_1_REMAP_HI		0x0348
#define	GT64260_CPU_PCI_1_MEM_2_REMAP_LO		0x0310
#define	GT64260_CPU_PCI_1_MEM_2_REMAP_HI		0x0350
#define	GT64260_CPU_PCI_1_MEM_3_REMAP_LO		0x0318
#define	GT64260_CPU_PCI_1_MEM_3_REMAP_HI		0x0358

/* CPU Control Registers */
#define GT64260_CPU_CONFIG				0x0000
#define GT64260_CPU_MODE				0x0120
#define GT64260_CPU_MASTER_CNTL				0x0160
#define GT64260_CPU_XBAR_CNTL_LO			0x0150
#define GT64260_CPU_XBAR_CNTL_HI			0x0158
#define GT64260_CPU_XBAR_TO				0x0168
#define GT64260_CPU_RR_XBAR_CNTL_LO			0x0170
#define GT64260_CPU_RR_XBAR_CNTL_HI			0x0178

/* CPU Sync Barrier Registers */
#define GT64260_CPU_SYNC_BARRIER_PCI_0			0x00c0
#define GT64260_CPU_SYNC_BARRIER_PCI_1			0x00c8

/* CPU Access Protection Registers */
#define	GT64260_CPU_PROT_WINDOWS			8

#define	GT64260_CPU_PROT_ACCPROTECT			(1<<16)
#define	GT64260_CPU_PROT_WRPROTECT			(1<<17)
#define	GT64260_CPU_PROT_CACHEPROTECT			(1<<18)

#define GT64260_CPU_PROT_BASE_0				0x0180
#define GT64260_CPU_PROT_TOP_0				0x0188
#define GT64260_CPU_PROT_BASE_1				0x0190
#define GT64260_CPU_PROT_TOP_1				0x0198
#define GT64260_CPU_PROT_BASE_2				0x01a0
#define GT64260_CPU_PROT_TOP_2				0x01a8
#define GT64260_CPU_PROT_BASE_3				0x01b0
#define GT64260_CPU_PROT_TOP_3				0x01b8
#define GT64260_CPU_PROT_BASE_4				0x01c0
#define GT64260_CPU_PROT_TOP_4				0x01c8
#define GT64260_CPU_PROT_BASE_5				0x01d0
#define GT64260_CPU_PROT_TOP_5				0x01d8
#define GT64260_CPU_PROT_BASE_6				0x01e0
#define GT64260_CPU_PROT_TOP_6				0x01e8
#define GT64260_CPU_PROT_BASE_7				0x01f0
#define GT64260_CPU_PROT_TOP_7				0x01f8

/* CPU Snoop Control Registers */
#define	GT64260_CPU_SNOOP_WINDOWS			4

#define	GT64260_CPU_SNOOP_NONE				0x00000000
#define	GT64260_CPU_SNOOP_WT				0x00010000
#define	GT64260_CPU_SNOOP_WB				0x00020000
#define	GT64260_CPU_SNOOP_MASK				0x00030000
#define	GT64260_CPU_SNOOP_ALL_BITS			GT64260_CPU_SNOOP_MASK

#define GT64260_CPU_SNOOP_BASE_0			0x0380
#define GT64260_CPU_SNOOP_TOP_0				0x0388
#define GT64260_CPU_SNOOP_BASE_1			0x0390
#define GT64260_CPU_SNOOP_TOP_1				0x0398
#define GT64260_CPU_SNOOP_BASE_2			0x03a0
#define GT64260_CPU_SNOOP_TOP_2				0x03a8
#define GT64260_CPU_SNOOP_BASE_3			0x03b0
#define GT64260_CPU_SNOOP_TOP_3				0x03b8

/* CPU Error Report Registers */
#define GT64260_CPU_ERR_ADDR_LO				0x0070
#define GT64260_CPU_ERR_ADDR_HI				0x0078
#define GT64260_CPU_ERR_DATA_LO				0x0128
#define GT64260_CPU_ERR_DATA_HI				0x0130
#define GT64260_CPU_ERR_PARITY				0x0138
#define GT64260_CPU_ERR_CAUSE				0x0140
#define GT64260_CPU_ERR_MASK				0x0148


/*
 *****************************************************************************
 *
 *	SDRAM Cotnroller Registers
 *
 *****************************************************************************
 */

/* SDRAM Config Registers */
#define	GT64260_SDRAM_CONFIG				0x0448
#define	GT64260_SDRAM_OPERATION_MODE			0x0474
#define	GT64260_SDRAM_ADDR_CNTL				0x047c
#define	GT64260_SDRAM_TIMING_PARAMS			0x04b4
#define	GT64260_SDRAM_UMA_CNTL				0x04a4
#define	GT64260_SDRAM_XBAR_CNTL_LO			0x04a8
#define	GT64260_SDRAM_XBAR_CNTL_HI			0x04ac
#define	GT64260_SDRAM_XBAR_CNTL_TO			0x04b0

/* SDRAM Banks Parameters Registers */
#define	GT64260_SDRAM_BANK_PARAMS_0			0x044c
#define	GT64260_SDRAM_BANK_PARAMS_1			0x0450
#define	GT64260_SDRAM_BANK_PARAMS_2			0x0454
#define	GT64260_SDRAM_BANK_PARAMS_3			0x0458

/* SDRAM Error Report Registers */
#define	GT64260_SDRAM_ERR_DATA_LO			0x0484
#define	GT64260_SDRAM_ERR_DATA_HI			0x0480
#define	GT64260_SDRAM_ERR_ADDR				0x0490
#define	GT64260_SDRAM_ERR_ECC_RCVD			0x0488
#define	GT64260_SDRAM_ERR_ECC_CALC			0x048c
#define	GT64260_SDRAM_ERR_ECC_CNTL			0x0494
#define	GT64260_SDRAM_ERR_ECC_ERR_CNT			0x0498


/*
 *****************************************************************************
 *
 *	Device/BOOT Cotnroller Registers
 *
 *****************************************************************************
 */

/* Device Control Registers */
#define	GT64260_DEV_BANK_PARAMS_0			0x045c
#define	GT64260_DEV_BANK_PARAMS_1			0x0460
#define	GT64260_DEV_BANK_PARAMS_2			0x0464
#define	GT64260_DEV_BANK_PARAMS_3			0x0468
#define	GT64260_DEV_BOOT_PARAMS				0x046c
#define	GT64260_DEV_IF_CNTL				0x04c0
#define	GT64260_DEV_IF_XBAR_CNTL_LO			0x04c8
#define	GT64260_DEV_IF_XBAR_CNTL_HI			0x04cc
#define	GT64260_DEV_IF_XBAR_CNTL_TO			0x04c4

/* Device Interrupt Registers */
#define	GT64260_DEV_INTR_CAUSE				0x04d0
#define	GT64260_DEV_INTR_MASK				0x04d4
#define	GT64260_DEV_INTR_ERR_ADDR			0x04d8


/*
 *****************************************************************************
 *
 *	PCI Bridge Interface Registers
 *
 *****************************************************************************
 */

/* PCI Configuration Access Registers */
#define	GT64260_PCI_0_CONFIG_ADDR			0x0cf8
#define	GT64260_PCI_0_CONFIG_DATA			0x0cfc
#define	GT64260_PCI_0_IACK				0x0c34

#define	GT64260_PCI_1_CONFIG_ADDR			0x0c78
#define	GT64260_PCI_1_CONFIG_DATA			0x0c7c
#define	GT64260_PCI_1_IACK				0x0cb4

/* PCI Control Registers */
#define	GT64260_PCI_0_CMD				0x0c00
#define	GT64260_PCI_0_MODE				0x0d00
#define	GT64260_PCI_0_TO_RETRY				0x0c04
#define	GT64260_PCI_0_RD_BUF_DISCARD_TIMER		0x0d04
#define	GT64260_PCI_0_MSI_TRIGGER_TIMER			0x0c38
#define	GT64260_PCI_0_ARBITER_CNTL			0x1d00
#define	GT64260_PCI_0_XBAR_CNTL_LO			0x1d08
#define	GT64260_PCI_0_XBAR_CNTL_HI			0x1d0c
#define	GT64260_PCI_0_XBAR_CNTL_TO			0x1d04
#define	GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO		0x1d18
#define	GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI		0x1d1c
#define	GT64260_PCI_0_SYNC_BARRIER			0x1d10
#define	GT64260_PCI_0_P2P_CONFIG			0x1d14
#define	GT64260_PCI_0_P2P_SWAP_CNTL			0x1d54

#define	GT64260_PCI_1_CMD				0x0c80
#define	GT64260_PCI_1_MODE				0x0d80
#define	GT64260_PCI_1_TO_RETRY				0x0c84
#define	GT64260_PCI_1_RD_BUF_DISCARD_TIMER		0x0d84
#define	GT64260_PCI_1_MSI_TRIGGER_TIMER			0x0cb8
#define	GT64260_PCI_1_ARBITER_CNTL			0x1d80
#define	GT64260_PCI_1_XBAR_CNTL_LO			0x1d88
#define	GT64260_PCI_1_XBAR_CNTL_HI			0x1d8c
#define	GT64260_PCI_1_XBAR_CNTL_TO			0x1d84
#define	GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO		0x1d98
#define	GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI		0x1d9c
#define	GT64260_PCI_1_SYNC_BARRIER			0x1d90
#define	GT64260_PCI_1_P2P_CONFIG			0x1d94
#define	GT64260_PCI_1_P2P_SWAP_CNTL			0x1dd4

/* PCI Access Control Regions Registers */
#define	GT64260_PCI_ACC_CNTL_WINDOWS			8

#define	GT64260_PCI_ACC_CNTL_PREFETCHEN			(1<<12)
#define	GT64260_PCI_ACC_CNTL_DREADEN			(1<<13)
#define	GT64260_PCI_ACC_CNTL_RDPREFETCH			(1<<16)
#define	GT64260_PCI_ACC_CNTL_RDLINEPREFETCH		(1<<17)
#define	GT64260_PCI_ACC_CNTL_RDMULPREFETCH		(1<<18)
#define	GT64260_PCI_ACC_CNTL_MBURST_4_WORDS		0x00000000
#define	GT64260_PCI_ACC_CNTL_MBURST_8_WORDS		0x00100000
#define	GT64260_PCI_ACC_CNTL_MBURST_16_WORDS		0x00200000
#define	GT64260_PCI_ACC_CNTL_MBURST_MASK		0x00300000
#define	GT64260_PCI_ACC_CNTL_SWAP_BYTE			0x00000000
#define	GT64260_PCI_ACC_CNTL_SWAP_NONE			0x01000000
#define	GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD		0x02000000
#define	GT64260_PCI_ACC_CNTL_SWAP_WORD			0x03000000
#define	GT64260_PCI_ACC_CNTL_SWAP_MASK			0x03000000
#define	GT64260_PCI_ACC_CNTL_ACCPROT			(1<<28)
#define	GT64260_PCI_ACC_CNTL_WRPROT			(1<<29)

#define	GT64260_PCI_ACC_CNTL_ALL_BITS	(GT64260_PCI_ACC_CNTL_PREFETCHEN |    \
					 GT64260_PCI_ACC_CNTL_DREADEN |       \
					 GT64260_PCI_ACC_CNTL_RDPREFETCH |    \
					 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
					 GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
					 GT64260_PCI_ACC_CNTL_MBURST_MASK |   \
					 GT64260_PCI_ACC_CNTL_SWAP_MASK |     \
					 GT64260_PCI_ACC_CNTL_ACCPROT|        \
					 GT64260_PCI_ACC_CNTL_WRPROT)

#define	GT64260_PCI_0_ACC_CNTL_0_BASE_LO		0x1e00
#define	GT64260_PCI_0_ACC_CNTL_0_BASE_HI		0x1e04
#define	GT64260_PCI_0_ACC_CNTL_0_TOP			0x1e08
#define	GT64260_PCI_0_ACC_CNTL_1_BASE_LO		0x1e10
#define	GT64260_PCI_0_ACC_CNTL_1_BASE_HI		0x1e14
#define	GT64260_PCI_0_ACC_CNTL_1_TOP			0x1e18
#define	GT64260_PCI_0_ACC_CNTL_2_BASE_LO		0x1e20
#define	GT64260_PCI_0_ACC_CNTL_2_BASE_HI		0x1e24
#define	GT64260_PCI_0_ACC_CNTL_2_TOP			0x1e28
#define	GT64260_PCI_0_ACC_CNTL_3_BASE_LO		0x1e30
#define	GT64260_PCI_0_ACC_CNTL_3_BASE_HI		0x1e34
#define	GT64260_PCI_0_ACC_CNTL_3_TOP			0x1e38
#define	GT64260_PCI_0_ACC_CNTL_4_BASE_LO		0x1e40
#define	GT64260_PCI_0_ACC_CNTL_4_BASE_HI		0x1e44
#define	GT64260_PCI_0_ACC_CNTL_4_TOP			0x1e48
#define	GT64260_PCI_0_ACC_CNTL_5_BASE_LO		0x1e50
#define	GT64260_PCI_0_ACC_CNTL_5_BASE_HI		0x1e54
#define	GT64260_PCI_0_ACC_CNTL_5_TOP			0x1e58
#define	GT64260_PCI_0_ACC_CNTL_6_BASE_LO		0x1e60
#define	GT64260_PCI_0_ACC_CNTL_6_BASE_HI		0x1e64
#define	GT64260_PCI_0_ACC_CNTL_6_TOP			0x1e68
#define	GT64260_PCI_0_ACC_CNTL_7_BASE_LO		0x1e70
#define	GT64260_PCI_0_ACC_CNTL_7_BASE_HI		0x1e74
#define	GT64260_PCI_0_ACC_CNTL_7_TOP			0x1e78

#define	GT64260_PCI_1_ACC_CNTL_0_BASE_LO		0x1e80
#define	GT64260_PCI_1_ACC_CNTL_0_BASE_HI		0x1e84
#define	GT64260_PCI_1_ACC_CNTL_0_TOP			0x1e88
#define	GT64260_PCI_1_ACC_CNTL_1_BASE_LO		0x1e90
#define	GT64260_PCI_1_ACC_CNTL_1_BASE_HI		0x1e94
#define	GT64260_PCI_1_ACC_CNTL_1_TOP			0x1e98
#define	GT64260_PCI_1_ACC_CNTL_2_BASE_LO		0x1ea0
#define	GT64260_PCI_1_ACC_CNTL_2_BASE_HI		0x1ea4
#define	GT64260_PCI_1_ACC_CNTL_2_TOP			0x1ea8
#define	GT64260_PCI_1_ACC_CNTL_3_BASE_LO		0x1eb0
#define	GT64260_PCI_1_ACC_CNTL_3_BASE_HI		0x1eb4
#define	GT64260_PCI_1_ACC_CNTL_3_TOP			0x1eb8
#define	GT64260_PCI_1_ACC_CNTL_4_BASE_LO		0x1ec0
#define	GT64260_PCI_1_ACC_CNTL_4_BASE_HI		0x1ec4
#define	GT64260_PCI_1_ACC_CNTL_4_TOP			0x1ec8
#define	GT64260_PCI_1_ACC_CNTL_5_BASE_LO		0x1ed0
#define	GT64260_PCI_1_ACC_CNTL_5_BASE_HI		0x1ed4
#define	GT64260_PCI_1_ACC_CNTL_5_TOP			0x1ed8
#define	GT64260_PCI_1_ACC_CNTL_6_BASE_LO		0x1ee0
#define	GT64260_PCI_1_ACC_CNTL_6_BASE_HI		0x1ee4
#define	GT64260_PCI_1_ACC_CNTL_6_TOP			0x1ee8
#define	GT64260_PCI_1_ACC_CNTL_7_BASE_LO		0x1ef0
#define	GT64260_PCI_1_ACC_CNTL_7_BASE_HI		0x1ef4
#define	GT64260_PCI_1_ACC_CNTL_7_TOP			0x1ef8

/* PCI Snoop Control Registers */
#define	GT64260_PCI_SNOOP_WINDOWS			4

#define	GT64260_PCI_SNOOP_NONE				0x00000000
#define	GT64260_PCI_SNOOP_WT				0x00001000
#define	GT64260_PCI_SNOOP_WB				0x00002000

#define	GT64260_PCI_0_SNOOP_0_BASE_LO			0x1f00
#define	GT64260_PCI_0_SNOOP_0_BASE_HI			0x1f04
#define	GT64260_PCI_0_SNOOP_0_TOP			0x1f08
#define	GT64260_PCI_0_SNOOP_1_BASE_LO			0x1f10
#define	GT64260_PCI_0_SNOOP_1_BASE_HI			0x1f14
#define	GT64260_PCI_0_SNOOP_1_TOP			0x1f18
#define	GT64260_PCI_0_SNOOP_2_BASE_LO			0x1f20
#define	GT64260_PCI_0_SNOOP_2_BASE