path: root/include/asm-powerpc/spu.h

/*
 * SPU core / file system interface and HW structures
 *
 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
 *
 * Author: Arnd Bergmann <arndb@de.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _SPU_H
#define _SPU_H
#ifdef __KERNEL__

#include <linux/workqueue.h>
#include <linux/sysdev.h>

#define LS_SIZE (256 * 1024)
#define LS_ADDR_MASK (LS_SIZE - 1)

#define MFC_PUT_CMD             0x20
#define MFC_PUTS_CMD            0x28
#define MFC_PUTR_CMD            0x30
#define MFC_PUTF_CMD            0x22
#define MFC_PUTB_CMD            0x21
#define MFC_PUTFS_CMD           0x2A
#define MFC_PUTBS_CMD           0x29
#define MFC_PUTRF_CMD           0x32
#define MFC_PUTRB_CMD           0x31
#define MFC_PUTL_CMD            0x24
#define MFC_PUTRL_CMD           0x34
#define MFC_PUTLF_CMD           0x26
#define MFC_PUTLB_CMD           0x25
#define MFC_PUTRLF_CMD          0x36
#define MFC_PUTRLB_CMD          0x35

#define MFC_GET_CMD             0x40
#define MFC_GETS_CMD            0x48
#define MFC_GETF_CMD            0x42
#define MFC_GETB_CMD            0x41
#define MFC_GETFS_CMD           0x4A
#define MFC_GETBS_CMD           0x49
#define MFC_GETL_CMD            0x44
#define MFC_GETLF_CMD           0x46
#define MFC_GETLB_CMD           0x45

#define MFC_SDCRT_CMD           0x80
#define MFC_SDCRTST_CMD         0x81
#define MFC_SDCRZ_CMD           0x89
#define MFC_SDCRS_CMD           0x8D
#define MFC_SDCRF_CMD           0x8F

#define MFC_GETLLAR_CMD         0xD0
#define MFC_PUTLLC_CMD          0xB4
#define MFC_PUTLLUC_CMD         0xB0
#define MFC_PUTQLLUC_CMD        0xB8
#define MFC_SNDSIG_CMD          0xA0
#define MFC_SNDSIGB_CMD         0xA1
#define MFC_SNDSIGF_CMD         0xA2
#define MFC_BARRIER_CMD         0xC0
#define MFC_EIEIO_CMD           0xC8
#define MFC_SYNC_CMD            0xCC

#define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
#define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
#define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
#define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
#define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
#define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
#define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
#define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */

#define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))

/* Events for Channels 0-2 */
#define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
#define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
#define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
#define MFC_DECREMENTER_EVENT               0x00000020
#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
#define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
#define MFC_SIGNAL_2_EVENT                  0x00000100
#define MFC_SIGNAL_1_EVENT                  0x00000200
#define MFC_LLR_LOST_EVENT                  0x00000400
#define MFC_PRIV_ATTN_EVENT                 0x00000800
#define MFC_MULTI_SRC_EVENT                 0x00001000

/* Flags indicating progress during context switch. */
#define SPU_CONTEXT_SWITCH_PENDING	0UL
#define SPU_CONTEXT_SWITCH_ACTIVE	1UL

struct spu_context;
struct spu_runqueue;

struct spu {
	const char *name;
	unsigned long local_store_phys;
	u8 *local_store;
	unsigned long problem_phys;
	struct spu_problem __iomem *problem;
	struct spu_priv1 __iomem *priv1;
	struct spu_priv2 __iomem *priv2;
	struct list_head list;
	struct list_head sched_list;
	int number;
	int nid;
	unsigned int irqs[3];
	u32 isrc;
	u32 node;
	u64 flags;
	u64 dar;
	u64 dsisr;
	size_t ls_size;
	unsigned int slb_replace;
	struct mm_struct *mm;
	struct spu_context *ctx;
	struct spu_runqueue *rq;
	unsigned long long timestamp;
	pid_t pid;
	int prio;
	int class_0_pending;
	spinlock_t register_lock;

	void (* wbox_callback)(struct spu *spu);
	void (* ibox_callback)(struct spu *spu);
	void (* stop_callback)(struct spu *spu);
	void (* mfc_callback)(struct spu *spu);
	void (* dma_callback)(struct spu *spu, int type);

	char irq_c0[8];
	char irq_c1[8];
	char irq_c2[8];

	struct sys_device sysdev;
};

struct spu *spu_alloc(void);
struct spu *spu_alloc_node(int node);
void spu_free(struct spu *spu);
int spu_irq_class_0_bottom(struct spu *spu);
int spu_irq_class_1_bottom(struct spu *spu);
void spu_irq_setaffinity(struct spu *spu, int cpu);

/* system callbacks from the SPU */
struct spu_syscall_block {
	u64 nr_ret;
	u64 parm[6];
};
extern long spu_sys_callback(struct spu_syscall_block *s);

/* syscalls implemented in spufs */
extern struct spufs_calls {
	asmlinkage long (*create_thread)(const char __user *name,
					unsigned int flags, mode_t mode);
	asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
						__u32 __user *ustatus);
	struct module *owner;
} spufs_calls;

/* return status from spu_run, same as in libspe */
#define SPE_EVENT_DMA_ALIGNMENT		0x0008	/*A DMA alignment error */
#define SPE_EVENT_SPE_ERROR		0x0010	/*An illegal instruction error*/
#define SPE_EVENT_SPE_DATA_SEGMENT	0x0020	/*A DMA segmentation error    */
#define SPE_EVENT_SPE_DATA_STORAGE	0x0040	/*A DMA storage error */
#define SPE_EVENT_INVALID_DMA		0x0800	/* Invalid MFC DMA */

/*
 * Flags for sys_spu_create.
 */
#define SPU_CREATE_EVENTS_ENABLED	0x0001
#define SPU_CREATE_GANG			0x0002

#define SPU_CREATE_FLAG_ALL		0x0003 /* mask of all valid flags */


#ifdef CONFIG_SPU_FS_MODULE
int register_spu_syscalls(struct spufs_calls *calls);
void unregister_spu_syscalls(struct spufs_calls *calls);
#else
static inline int register_spu_syscalls(struct spufs_calls *calls)
{
	return 0;
}
static inline void unregister_spu_syscalls(struct spufs_calls *calls)
{
}
#endif /* MODULE */


/*
 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
 */

union mfc_tag_size_class_cmd {
	struct {
		u16 mfc_size;
		u16 mfc_tag;
		u8  pad;
		u8  mfc_rclassid;
		u16 mfc_cmd;
	} u;
	struct {
		u32 mfc_size_tag32;
		u32 mfc_class_cmd32;
	} by32;
	u64 all64;
};

struct mfc_cq_sr {
	u64 mfc_cq_data0_RW;
	u64 mfc_cq_data1_RW;
	u64 mfc_cq_data2_RW;
	u64 mfc_cq_data3_RW;
};

struct spu_problem {
#define MS_SYNC_PENDING         1L
	u64 spc_mssync_RW;					/* 0x0000 */
	u8  pad_0x0008_0x3000[0x3000 - 0x0008];

	/* DMA Area */
	u8  pad_0x3000_0x3004[0x4];				/* 0x3000 */
	u32 mfc_lsa_W;						/* 0x3004 */
	u64 mfc_ea_W;						/* 0x3008 */
	union mfc_tag_size_class_cmd mfc_union_W;			/* 0x3010 */
	u8  pad_0x3018_0x3104[0xec];				/* 0x3018 */
	u32 dma_qstatus_R;					/* 0x3104 */
	u8  pad_0x3108_0x3204[0xfc];				/* 0x3108 */
	u32 dma_querytype_RW;					/* 0x3204 */
	u8  pad_0x3208_0x321c[0x14];				/* 0x3208 */
	u32 dma_querymask_RW;					/* 0x321c */
	u8  pad_0x3220_0x322c[0xc];				/* 0x3220 */
	u32 dma_tagstatus_R;					/* 0x322c */
#define DMA_TAGSTATUS_INTR_ANY	1u
#define DMA_TAGSTATUS_INTR_ALL	2u
	u8  pad_0x3230_0x4000[0x4000 - 0x3230]; 		/* 0x3230 */

	/* SPU Control Area */
	u8  pad_0x4000_0x4004[0x4];				/* 0x4000 */
	u32 pu_mb_R;						/* 0x4004 */
	u8  pad_0x4008_0x400c[0x4];				/* 0x4008 */
	u32 spu_mb_W;						/* 0x400c */
	u8  pad_0x4010_0x4014[0x4];				/* 0x4010 */
	u32 mb_stat_R;						/* 0x4014 */
	u8  pad_0x4018_0x401c[0x4];				/* 0x4018 */
	u32 spu_runcntl_RW;					/* 0x401c */
#define SPU_RUNCNTL_STOP	0L
#define SPU_RUNCNTL_RUNNABLE	1L
	u8  pad_0x4020_0x4024[0x4];				/* 0x4020 */
	u32 spu_status_R;					/* 0x4024 */
#define SPU_STOP_STATUS_SHIFT           16
#define SPU_STATUS_STOPPED		0x0
#define SPU_STATUS_RUNNING		0x1
#define SPU_STATUS_STOPPED_BY_STOP	0x2
#define SPU_STATUS_STOPPED_BY_HALT	0x4
#define SPU_STATUS_WAITING_FOR_CHANNEL	0x8
#define SPU_STATUS_SINGLE_STEP		0x10
#define SPU_STATUS_INVALID_INSTR        0x20
#define SPU_STATUS_INVALID_CH           0x40
#define SPU_STATUS_ISOLATED_STATE       0x80
#define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200
#define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400
	u8  pad_0x4028_0x402c[0x4];				/* 0x4028 */
	u32 spu_spe_R;						/* 0x402c */
	u8  pad_0x4030_0x4034[0x4];				/* 0x4030 */
	u32 spu_npc_RW;						/* 0x4034 */
	u8  pad_0x4038_0x14000[0x14000 - 0x4038];		/* 0x4038 */

	/* Signal Notification Area */
	u8  pad_0x14000_0x1400c[0xc];				/* 0x14000 */
	u32 signal_notify1;					/* 0x1400c */
	u8  pad_0x14010_0x1c00c[0x7ffc];			/* 0x14010 */
	u32 signal_notify2;					/* 0x1c00c */
} __attribute__ ((aligned(0x20000)));

/* SPU Privilege 2 State Area */
struct spu_priv2 {
	/* MFC Registers */
	u8  pad_0x0000_0x1100[0x1100 - 0x0000]; 		/* 0x0000 */

	/* SLB Management Registers */
	u8  pad_0x1100_0x1108[0x8];				/* 0x1100 */
	u64 slb_index_W;					/* 0x1108 */
#define SLB_INDEX_MASK				0x7L
	u64 slb_esid_RW;					/* 0x1110 */
	u64 slb_vsid_RW;					/* 0x1118 */
#define SLB_VSID_SUPERVISOR_STATE	(0x1ull << 11)
#define SLB_VSID_SUPERVISOR_STATE_MASK	(0x1ull << 11)
#define SLB_VSID_PROBLEM_STATE		(0x1ull << 10)
#define SLB_VSID_PROBLEM_STATE_MASK	(0x1ull << 10)
#define SLB_VSID_EXECUTE_SEGMENT	(0x1ull << 9)
#define SLB_VSID_NO_EXECUTE_SEGMENT	(0x1ull << 9)
#define SLB_VSID_EXECUTE_SEGMENT_MASK	(0x1ull << 9)
#define SLB_VSID_4K_PAGE		(0x0 << 8)
#define SLB_VSID_LARGE_PAGE		(0x1ull << 8)
#define SLB_VSID_PAGE_SIZE_MASK		(0x1ull << 8)
#define SLB_VSID_CLASS_MASK		(0x1ull &l