path: root/include/asm-mips/sibyte/sb1250_regs.h

/*  *********************************************************************
    *  SB1250 Board Support Package
    *
    *  Register Definitions                     File: sb1250_regs.h
    *
    *  This module contains the addresses of the on-chip peripherals
    *  on the SB1250.
    *
    *  SB1250 specification level:  01/02/2002
    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
    *  Broadcom Corporation. All rights reserved.
    *
    *  This program is free software; you can redistribute it and/or
    *  modify it under the terms of the GNU General Public License as
    *  published by the Free Software Foundation; either version 2 of
    *  the License, or (at your option) any later version.
    *
    *  This program is distributed in the hope that it will be useful,
    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    *  GNU General Public License for more details.
    *
    *  You should have received a copy of the GNU General Public License
    *  along with this program; if not, write to the Free Software
    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    *  MA 02111-1307 USA
    ********************************************************************* */


#ifndef _SB1250_REGS_H
#define _SB1250_REGS_H

#include "sb1250_defs.h"


/*  *********************************************************************
    *  Some general notes:
    *
    *  For the most part, when there is more than one peripheral
    *  of the same type on the SOC, the constants below will be
    *  offsets from the base of each peripheral.  For example,
    *  the MAC registers are described as offsets from the first
    *  MAC register, and there will be a MAC_REGISTER() macro
    *  to calculate the base address of a given MAC.
    *
    *  The information in this file is based on the SB1250 SOC
    *  manual version 0.2, July 2000.
    ********************************************************************* */


/*  *********************************************************************
    * Memory Controller Registers
    ********************************************************************* */

/*
 * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
 * since there is one reg there (but it could get its addr/offset constant).
 */

#if SIBYTE_HDR_FEATURE_1250_112x		/* This MC only on 1250 & 112x */
#define A_MC_BASE_0                 0x0010051000
#define A_MC_BASE_1                 0x0010052000
#define MC_REGISTER_SPACING         0x1000

#define A_MC_BASE(ctlid)            ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
#define A_MC_REGISTER(ctlid,reg)    (A_MC_BASE(ctlid)+(reg))

#define R_MC_CONFIG                 0x0000000100
#define R_MC_DRAMCMD                0x0000000120
#define R_MC_DRAMMODE               0x0000000140
#define R_MC_TIMING1                0x0000000160
#define R_MC_TIMING2                0x0000000180
#define R_MC_CS_START               0x00000001A0
#define R_MC_CS_END                 0x00000001C0
#define R_MC_CS_INTERLEAVE          0x00000001E0
#define S_MC_CS_STARTEND            16

#define R_MC_CSX_BASE               0x0000000200
#define R_MC_CSX_ROW                0x0000000000	/* relative to CSX_BASE, above */
#define R_MC_CSX_COL                0x0000000020	/* relative to CSX_BASE, above */
#define R_MC_CSX_BA                 0x0000000040	/* relative to CSX_BASE, above */
#define MC_CSX_SPACING              0x0000000060	/* relative to CSX_BASE, above */

#define R_MC_CS0_ROW                0x0000000200
#define R_MC_CS0_COL                0x0000000220
#define R_MC_CS0_BA                 0x0000000240
#define R_MC_CS1_ROW                0x0000000260
#define R_MC_CS1_COL                0x0000000280
#define R_MC_CS1_BA                 0x00000002A0
#define R_MC_CS2_ROW                0x00000002C0
#define R_MC_CS2_COL                0x00000002E0
#define R_MC_CS2_BA                 0x0000000300
#define R_MC_CS3_ROW                0x0000000320
#define R_MC_CS3_COL                0x0000000340
#define R_MC_CS3_BA                 0x0000000360
#define R_MC_CS_ATTR                0x0000000380
#define R_MC_TEST_DATA              0x0000000400
#define R_MC_TEST_ECC               0x0000000420
#define R_MC_MCLK_CFG               0x0000000500

#endif	/* 1250 & 112x */

/*  *********************************************************************
    * L2 Cache Control Registers
    ********************************************************************* */

#if SIBYTE_HDR_FEATURE_1250_112x	/* This L2C only on 1250/112x */

#define A_L2_READ_TAG               0x0010040018
#define A_L2_ECC_TAG                0x0010040038
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_READ_MISC              0x0010040058
#endif /* 1250 PASS3 || 112x PASS1 */
#define A_L2_WAY_DISABLE            0x0010041000
#define A_L2_MAKEDISABLE(x)         (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
#define A_L2_MGMT_TAG_BASE          0x00D0000000

#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_CACHE_DISABLE	   0x0010042000
#define A_L2_MAKECACHEDISABLE(x)   (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
#define A_L2_MISC_CONFIG	   0x0010043000
#endif /* 1250 PASS2 || 112x PASS1 */

/* Backward-compatibility definitions.  */
/* XXX: discourage people from using these constants.  */
#define A_L2_READ_ADDRESS           A_L2_READ_TAG
#define A_L2_EEC_ADDRESS            A_L2_ECC_TAG

#endif


/*  *********************************************************************
    * PCI Interface Registers
    ********************************************************************* */

#if SIBYTE_HDR_FEATURE_1250_112x	/* This PCI/HT only on 1250/112x */
#define A_PCI_TYPE00_HEADER         0x00DE000000
#define A_PCI_TYPE01_HEADER         0x00DE000800
#endif


/*  *********************************************************************
    * Ethernet DMA and MACs
    ********************************************************************* */

#define A_MAC_BASE_0                0x0010064000
#define A_MAC_BASE_1                0x0010065000
#if SIBYTE_HDR_FEATURE_CHIP(1250)
#define A_MAC_BASE_2                0x0010066000
#endif /* 1250 */

#define MAC_SPACING                 0x1000
#define MAC_DMA_TXRX_SPACING        0x0400
#define MAC_DMA_CHANNEL_SPACING     0x0100
#define DMA_RX                      0
#define DMA_TX                      1
#define MAC_NUM_DMACHAN		    2		    /* channels per direction */

/* XXX: not correct; depends on SOC type.  */
#define MAC_NUM_PORTS               3

#define A_MAC_CHANNEL_BASE(macnum)                  \
            (A_MAC_BASE_0 +                         \
             MAC_SPACING*(macnum))

#define A_MAC_REGISTER(macnum,reg)                  \
            (A_MAC_BASE_0 +                         \
             MAC_SPACING*(macnum) + (reg))


#define R_MAC_DMA_CHANNELS		0x800 /* Relative to A_MAC_CHANNEL_BASE */

#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan)    \
             ((A_MAC_CHANNEL_BASE(macnum)) +        \
             R_MAC_DMA_CHANNELS +                   \
             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
             (MAC_DMA_CHANNEL_SPACING*(chan)))

#define R_MAC_DMA_CHANNEL_BASE(txrx,chan)    \
             (R_MAC_DMA_CHANNELS +                   \
             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
             (MAC_DMA_CHANNEL_SPACING*(chan)))

#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg)           \
            (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) +    \
            (reg))

#define R_MAC_DMA_REGISTER(txrx,chan,reg)           \
            (R_MAC_DMA_CHANNEL_BASE(txrx,chan) +    \
            (reg))

/*
 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
 */

#define R_MAC_DMA_CONFIG0               0x00000000
#define R_MAC_DMA_CONFIG1               0x00000008
#define R_MAC_DMA_DSCR_BASE             0x00000010
#define R_MAC_DMA_DSCR_CNT              0x00000018
#define R_MAC_DMA_CUR_DSCRA             0x00000020
#define R_MAC_DMA_CUR_DSCRB             0x00000028
#define R_MAC_DMA_CUR_DSCRADDR          0x00000030
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_DMA_OODPKTLOST_RX         0x00000038	/* rx only */
#endif /* 1250 PASS3 || 112x PASS1 */

/*
 * RMON Counters
 */

#define R_MAC_RMON_TX_BYTES             0x00000000
#define R_MAC_RMON_COLLISIONS           0x00000008
#define R_MAC_RMON_LATE_COL             0x00000010
#define R_MAC_RMON_EX_COL               0x00000018
#define R_MAC_RMON_FCS_ERROR            0x00000020
#define R_MAC_RMON_TX_ABORT             0x00000028
/* Counter #6 (0x30) now reserved */
#define R_MAC_RMON_TX_BAD               0x00000038
#define R_MAC_RMON_TX_GOOD              0x00000040
#define R_MAC_RMON_TX_RUNT              0x00000048
#define R_MAC_RMON_TX_OVERSIZE          0x00000050
#define R_MAC_RMON_RX_BYTES             0x00000080
#define R_MAC_RMON_RX_MCAST             0x00000088
#define R_MAC_RMON_RX_BCAST             0x00000090
#define R_MAC_RMON_RX_BAD               0x00000098
#define R_MAC_RMON_RX_GOOD              0x000000A0
#define R_MAC_RMON_RX_RUNT              0x000000A8
#define R_MAC_RMON_RX_OVERSIZE          0x000000B0
#define R_MAC_RMON_RX_FCS_ERROR         0x000000B8
#define R_MAC_RMON_RX_LENGTH_ERROR      0x000000C0
#define R_MAC_RMON_RX_CODE_ERROR        0x000000C8
#define R_MAC_RMON_RX_ALIGN_ERROR       0x000000D0

/* Updated to spec 0.2 */
#define R_MAC_CFG                       0x00000100
#define R_MAC_THRSH_CFG                 0x00000108
#define R_MAC_VLANTAG                   0x00000110
#define R_MAC_FRAMECFG                  0x00000118
#define R_MAC_EOPCNT                    0x00000120
#define R_MAC_FIFO_PTRS                 0x00000128
#define R_MAC_ADFILTER_CFG              0x00000200
#define R_MAC_ETHERNET_ADDR             0x00000208
#define R_MAC_PKT_TYPE                  0x00000210
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define R_MAC_ADMASK0			0x00000218
#define R_MAC_ADMASK1			0x00000220
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define R_MAC_HASH_BASE                 0x00000240
#define R_MAC_ADDR_BASE                 0x00000280
#define R_MAC_CHLO0_BASE                0x00000300
#define R_MAC_CHUP0_BASE                0x00000320
#define R_MAC_ENABLE                    0x00000400
#define R_MAC_STATUS                    0x00000408
#define R_MAC_INT_MASK                  0x00000410
#define R_MAC_TXD_CTL                   0x00000420
#define R_MAC_MDIO                      0x00000428
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define R_MAC_STATUS1		        0x00000430
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define R_MAC_DEBUG_STATUS              0x00000448

#define MAC_HASH_COUNT			8
#define MAC_ADDR_COUNT			8
#define MAC_CHMAP_COUNT			4


/*  *********************************************************************
    * DUART Registers
    ********************************************************************* */


#if SIBYTE_HDR_FEATURE_1250_112x		/* This MC only on 1250 & 112x */
#define R_DUART_NUM_PORTS           2

#define A_DUART                     0x0010060000

#define DUART_CHANREG_SPACING       0x100
#define A_DUART_CHANREG(chan,reg)   (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))
#define R_DUART_CHANREG(chan,reg)   (DUART_CHANREG_SPACING*(chan) + (reg))
#endif	/* 1250 & 112x */

#define R_DUART_MODE_REG_1	    0x100
#define R_DUART_MODE_REG_2	    0x110
#define R_DUART_STATUS              0x120
#define R_DUART_CLK_SEL             0x130
#define R_DUART_CMD                 0x150
#define R_DUART_RX_HOLD             0x160
#define R_DUART_TX_HOLD             0x170

#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define R_DUART_FULL_CTL	    0x140
#define R_DUART_OPCR_X		    0x180
#define R_DUART_AUXCTL_X	    0x190
#endif /* 1250 PASS2 || 112x PASS1 || 1480*/


/*
 * The IMR and ISR can't be addressed with A_DUART_CHANREG,
 * so use this macro instead.
 */

#define R_DUART_AUX_CTRL            0x310
#define R_DUART_ISR_A               0x320
#define R_DUART_IMR_A               0x330
#define R_DUART_ISR_B               0x340
#define R_DUART_IMR_B               0x350
#define R_DUART_OUT_PORT            0x360
#define R_DUART_OPCR                0x370
#define R_DUART_IN_PORT             0x380

#define R_DUART_SET_OPR		    0x3B0
#define R_DUART_CLEAR_OPR	    0x3C0

#define DUART_IMRISR_SPACING        0x20

#if SIBYTE_HDR_FEATURE_1250_112x		/* This MC only on 1250 & 112x */
#define R_DUART_IMRREG(chan)	    (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING)
#define R_DUART_ISRREG(chan)	    (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING)

#define A_DUART_IMRREG(chan)	    (A_DUART + R_DUART_IMRREG(chan))
#define A_DUART_ISRREG(chan)	    (A_DUART + R_DUART_ISRREG(chan))
#endif	/* 1250 & 112x */




/*
 * These constants are the absolute addresses.
 */

#define A_DUART_MODE_REG_1_A        0x0010060100
#define A_DUART_MODE_REG_2_A        0x0010060110
#define A_DUART_STATUS_A            0x0010060120
#define A_DUART_CLK_SEL_A           0x0010060130
#define A_DUART_CMD_A               0x0010060150
#define A_DUART_RX_HOLD_A           0x0010060160
#define A_DUART_TX_HOLD_A           0x0010060170

#define A_DUART_MODE_REG_1_B        0x0010060200
#define A_DUART_MODE_REG_2_B        0x0010060210
#define A_DUART_STATUS_B            0x0010060220
#define A_DUART_CLK_SEL_B           0x0010060230
#define A_DUART_CMD_B               0x0010060250
#define A_DUART_RX_HOLD_B           0x0010060260
#define A_DUART_TX_HOLD_B           0x0010060270

#define A_DUART_INPORT_CHNG         0x0010060300
#define A_DUART_AUX_CTRL            0x0010060310
#define A_DUART_ISR_A               0x0010060320
#define A_DUART_IMR_A               0x0010060330
#define A_DUART_ISR_B               0x0010060340
#define A_DUART_IMR_B               0x0010060350
#define A_DUART_OUT_PORT            0x0010060360
#define A_DUART_OPCR                0x0010060370
#define A_DUART_IN_PORT             0x0010060380
#define A_DUART_ISR                 0x0010060390
#define A_DUART_IMR                 0x00100603A0
#define A_DUART_SET_OPR             0x00100603B0
#define A_DUART_CLEAR_OPR           0x00100603C0
#define A_DUART_INPORT_CHNG_A       0x00100603D0
#define A_DUART_INPORT_CHNG_B       0x00100603E0

#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DUART_FULL_CTL_A	    0x0010060140
#define A_DUART_FULL_CTL_B	    0x0010060240

#define A_DUART_OPCR_A	  	    0x0010060180
#define A_DUART_OPCR_B	  	    0x0010060280

#define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
#endif /* 1250 PASS2 || 112x PASS1 */


/*  *********************************************************************
    * Synchronous Serial Registers
    ********************************************************************* */


#if SIBYTE_HDR_FEATURE_1250_112x	/* sync serial only on 1250/112x */

#define A_SER_BASE_0                0x0010060400
#define A_SER_BASE_1                0x0010060800
#define SER_SPACING                 0x400

#define SER_DMA_TXRX_SPACING        0x80

#define SER_NUM_PORTS               2

#define A_SER_CHANNEL_BASE(sernum)                  \
            (A_SER_BASE_0 +                         \
             SER_SPACING*(sernum))

#define A_SER_REGISTER(sernum,reg)                  \
            (A_SER_BASE_0 +                         \
             SER_SPACING*(sernum) + (reg))


#define R_SER_DMA_CHANNELS		0   /* Relative to A_SER_BASE_x */

#define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \
             ((A_SER_CHANNEL_BASE(sernum)) +        \
             R_SER_DMA_CHANNELS +                   \
             (SER_DMA_TXRX_SPACING*(txrx)))

#define A_SER_DMA_REGISTER(sernum,txrx,reg)           \
            (A_SER_DMA_CHANNEL_BASE(sernum,txrx) +    \
            (reg))


/*
 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
 */

#define R_SER_DMA_CONFIG0           0x00000000
#define R_SER_DMA_CONFIG1           0x00000008
#define R_SER_DMA_DSCR_BASE         0x00000010
#define R_SER_DMA_DSCR_CNT          0x00000018
#define R_SER_DMA_CUR_DSCRA         0x00000020
#define R_SER_DMA_CUR_DSCRB         0x00000028
#define R_SER_DMA_CUR_DSCRADDR      0x00000030

#define R_SER_DMA_CONFIG0_RX        0x00000000
#define R_SER_DMA_CONFIG1_RX        0x00000008
#define R_SER_DMA_DSCR_BASE_RX      0x00000010
#define R_SER_DMA_DSCR_COUNT_RX     0x00000018
#define R_SER_DMA_CUR_DSCR_A_RX     0x00000020
#define R_SER_DMA_CUR_DSCR_B_RX     0x00000028
#define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030

#define R_SER_DMA_CONFIG0_TX        0x00000080
#define R_SER_DMA_CONFIG1_TX        0x00000088
#define R_SER_DMA_DSCR_BASE_TX      0x00000090
#define R_SER_DMA_DSCR_COUNT_TX     0x00000098
#define R_SER_DMA_CUR_DSCR_A_TX     0x000000A0
#define R_SER_DMA_CUR_DSCR_B_TX     0x000000A8
#define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0

#define R_SER_MODE                  0x00000100
#define R_SER_MINFRM_SZ             0x00000108
#define R_SER_MAXFRM_SZ             0x00000110
#define R_SER_ADDR                  0x00000118
#define R_SER_USR0_ADDR             0x00000120
#define R_SER_USR1_ADDR             0x00000128
#define R_SER_USR2_ADDR             0x00000130
#define R_SER_USR3_ADDR             0x00000138
#define R_SER_CMD                   0x00000140
#de