path: root/include/asm-mips/sibyte/bcm1480_regs.h

/*  *********************************************************************
    *  BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
    *
    *  Register Definitions                     File: bcm1480_regs.h
    *
    *  This module contains the addresses of the on-chip peripherals
    *  on the BCM1280 and BCM1480.
    *
    *  BCM1480 specification level:  1X55_1X80-UM100-D4 (11/24/03)
    *
    *********************************************************************
    *
    *  Copyright 2000,2001,2002,2003
    *  Broadcom Corporation. All rights reserved.
    *
    *  This program is free software; you can redistribute it and/or
    *  modify it under the terms of the GNU General Public License as
    *  published by the Free Software Foundation; either version 2 of
    *  the License, or (at your option) any later version.
    *
    *  This program is distributed in the hope that it will be useful,
    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    *  GNU General Public License for more details.
    *
    *  You should have received a copy of the GNU General Public License
    *  along with this program; if not, write to the Free Software
    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    *  MA 02111-1307 USA
    ********************************************************************* */

#ifndef _BCM1480_REGS_H
#define _BCM1480_REGS_H

#include "sb1250_defs.h"

/*  *********************************************************************
    *  Pull in the BCM1250's registers since a great deal of the 1480's
    *  functions are the same as the BCM1250.
    ********************************************************************* */

#include "sb1250_regs.h"


/*  *********************************************************************
    *  Some general notes:
    *
    *  Register addresses are grouped by function and follow the order
    *  of the User Manual.
    *
    *  For the most part, when there is more than one peripheral
    *  of the same type on the SOC, the constants below will be
    *  offsets from the base of each peripheral.  For example,
    *  the MAC registers are described as offsets from the first
    *  MAC register, and there will be a MAC_REGISTER() macro
    *  to calculate the base address of a given MAC.
    *
    *  The information in this file is based on the BCM1X55/BCM1X80
    *  User Manual, Document 1X55_1X80-UM100-R, 22/12/03.
    *
    *  This file is basically a "what's new" header file.  Since the
    *  BCM1250 and the new BCM1480 (and derivatives) share many common
    *  features, this file contains only what's new or changed from
    *  the 1250.  (above, you can see that we include the 1250 symbols
    *  to get the base functionality).
    *
    *  In software, be sure to use the correct symbols, particularly
    *  for blocks that are different between the two chip families.
    *  All BCM1480-specific symbols have _BCM1480_ in their names,
    *  and all BCM1250-specific and "base" functions that are common in
    *  both chips have no special names (this is for compatibility with
    *  older include files).  Therefore, if you're working with the
    *  SCD, which is very different on each chip, A_SCD_xxx implies
    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
    *  version.
    ********************************************************************* */


/*  *********************************************************************
    * Memory Controller Registers (Section 6)
    ********************************************************************* */

#define A_BCM1480_MC_BASE_0                 0x0010050000
#define A_BCM1480_MC_BASE_1                 0x0010051000
#define A_BCM1480_MC_BASE_2                 0x0010052000
#define A_BCM1480_MC_BASE_3                 0x0010053000
#define BCM1480_MC_REGISTER_SPACING         0x1000

#define A_BCM1480_MC_BASE(ctlid)            (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
#define A_BCM1480_MC_REGISTER(ctlid,reg)    (A_BCM1480_MC_BASE(ctlid)+(reg))

#define R_BCM1480_MC_CONFIG                 0x0000000100
#define R_BCM1480_MC_CS_START               0x0000000120
#define R_BCM1480_MC_CS_END                 0x0000000140
#define S_BCM1480_MC_CS_STARTEND            24

#define R_BCM1480_MC_CS01_ROW0              0x0000000180
#define R_BCM1480_MC_CS01_ROW1              0x00000001A0
#define R_BCM1480_MC_CS23_ROW0              0x0000000200
#define R_BCM1480_MC_CS23_ROW1              0x0000000220
#define R_BCM1480_MC_CS01_COL0              0x0000000280
#define R_BCM1480_MC_CS01_COL1              0x00000002A0
#define R_BCM1480_MC_CS23_COL0              0x0000000300
#define R_BCM1480_MC_CS23_COL1              0x0000000320

#define R_BCM1480_MC_CSX_BASE               0x0000000180
#define R_BCM1480_MC_CSX_ROW0               0x0000000000   /* relative to CSX_BASE */
#define R_BCM1480_MC_CSX_ROW1               0x0000000020   /* relative to CSX_BASE */
#define R_BCM1480_MC_CSX_COL0               0x0000000100   /* relative to CSX_BASE */
#define R_BCM1480_MC_CSX_COL1               0x0000000120   /* relative to CSX_BASE */
#define BCM1480_MC_CSX_SPACING              0x0000000080   /* CS23 relative to CS01 */

#define R_BCM1480_MC_CS01_BA                0x0000000380
#define R_BCM1480_MC_CS23_BA                0x00000003A0
#define R_BCM1480_MC_DRAMCMD                0x0000000400
#define R_BCM1480_MC_DRAMMODE               0x0000000420
#define R_BCM1480_MC_CLOCK_CFG              0x0000000440
#define R_BCM1480_MC_MCLK_CFG               R_BCM1480_MC_CLOCK_CFG
#define R_BCM1480_MC_TEST_DATA              0x0000000480
#define R_BCM1480_MC_TEST_ECC               0x00000004A0
#define R_BCM1480_MC_TIMING1                0x00000004C0
#define R_BCM1480_MC_TIMING2                0x00000004E0
#define R_BCM1480_MC_DLL_CFG                0x0000000500
#define R_BCM1480_MC_DRIVE_CFG              0x0000000520

#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define R_BCM1480_MC_ODT		    0x0000000460
#define R_BCM1480_MC_ECC_STATUS		    0x0000000540
#endif

/* Global registers (single instance) */
#define A_BCM1480_MC_GLB_CONFIG             0x0010054100
#define A_BCM1480_MC_GLB_INTLV              0x0010054120
#define A_BCM1480_MC_GLB_ECC_STATUS         0x0010054140
#define A_BCM1480_MC_GLB_ECC_ADDR           0x0010054160
#define A_BCM1480_MC_GLB_ECC_CORRECT        0x0010054180
#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL   0x00100541A0

/*  *********************************************************************
    * L2 Cache Control Registers (Section 5)
    ********************************************************************* */

#define A_BCM1480_L2_BASE                   0x0010040000

#define A_BCM1480_L2_READ_TAG               0x0010040018
#define A_BCM1480_L2_ECC_TAG                0x0010040038
#define A_BCM1480_L2_MISC0_VALUE            0x0010040058
#define A_BCM1480_L2_MISC1_VALUE            0x0010040078
#define A_BCM1480_L2_MISC2_VALUE            0x0010040098
#define A_BCM1480_L2_MISC_CONFIG            0x0010040040	/* x040 */
#define A_BCM1480_L2_CACHE_DISABLE          0x0010040060	/* x060 */
#define A_BCM1480_L2_MAKECACHEDISABLE(x)    (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
#define A_BCM1480_L2_WAY_ENABLE_3_0         0x0010040080	/* x080 */
#define A_BCM1480_L2_WAY_ENABLE_7_4         0x00100400A0	/* x0A0 */
#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
#define A_BCM1480_L2_WAY_LOCAL_3_0          0x0010040100	/* x100 */
#define A_BCM1480_L2_WAY_LOCAL_7_4          0x0010040120	/* x120 */
#define A_BCM1480_L2_WAY_REMOTE_3_0         0x0010040140	/* x140 */
#define A_BCM1480_L2_WAY_REMOTE_7_4         0x0010040160	/* x160 */
#define A_BCM1480_L2_WAY_AGENT_3_0          0x00100400C0	/* xxC0 */
#define A_BCM1480_L2_WAY_AGENT_7_4          0x00100400E0	/* xxE0 */
#define A_BCM1480_L2_WAY_ENABLE(A, banks)   (A | (((~(banks))&0x0F) << 8))
#define A_BCM1480_L2_BANK_BASE              0x00D0300000
#define A_BCM1480_L2_BANK_ADDRESS(b)        (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
#define A_BCM1480_L2_MGMT_TAG_BASE          0x00D0000000


/*  *********************************************************************
    * PCI-X Interface Registers (Section 7)
    ********************************************************************* */

#define A_BCM1480_PCI_BASE                  0x0010061400

#define A_BCM1480_PCI_RESET                 0x0010061400
#define A_BCM1480_PCI_DLL                   0x0010061500

#define A_BCM1480_PCI_TYPE00_HEADER         0x002E000000

/*  *********************************************************************
    * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
    ********************************************************************* */

/* No register changes with Rev.C BCM1250, but one additional MAC */

#define A_BCM1480_MAC_BASE_2        0x0010066000

#ifndef A_MAC_BASE_2
#define A_MAC_BASE_2                A_BCM1480_MAC_BASE_2
#endif

#define A_BCM1480_MAC_BASE_3        0x0010067000
#define A_MAC_BASE_3                A_BCM1480_MAC_BASE_3

#define R_BCM1480_MAC_DMA_OODPKTLOST        0x00000038

#ifndef R_MAC_DMA_OODPKTLOST
#define R_MAC_DMA_OODPKTLOST        R_BCM1480_MAC_DMA_OODPKTLOST
#endif


/*  *********************************************************************
    * DUART Registers (Section 14)
    ********************************************************************* */

/* No significant differences from BCM1250, two DUARTs */

/*  Conventions, per user manual:
 *     DUART    generic, channels A,B,C,D
 *     DUART0   implementing channels A,B
 *     DUART1   inplementing channels C,D
 */

#define BCM1480_DUART_NUM_PORTS           4

#define A_BCM1480_DUART0                    0x0010060000
#define A_BCM1480_DUART1                    0x0010060400
#define A_BCM1480_DUART(chan)               ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)

#define BCM1480_DUART_CHANREG_SPACING       0x100
#define A_BCM1480_DUART_CHANREG(chan,reg)   (A_BCM1480_DUART(chan) \
                                     + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \
                                     + (reg))
#define R_BCM1480_DUART_CHANREG(chan,reg)   (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg))

#define R_BCM1480_DUART_IMRREG(chan)	    (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING)
#define R_BCM1480_DUART_ISRREG(chan)	    (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING)

#define A_BCM1480_DUART_IMRREG(chan)	    (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan))
#define A_BCM1480_DUART_ISRREG(chan)	    (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan))
#define A_BCM1480_DUART_IN_PORT(chan)       (A_BCM1480_DUART(chan) + R_DUART_INP_ORT)

/*
 * These constants are the absolute addresses.
 */

#define A_BCM1480_DUART_MODE_REG_1_C        0x0010060400
#define A_BCM1480_DUART_MODE_REG_2_C        0x0010060410
#define A_BCM1480_DUART_STATUS_C            0x0010060420
#define A_BCM1480_DUART_CLK_SEL_C           0x0010060430
#define A_BCM1480_DUART_FULL_CTL_C          0x0010060440
#define A_BCM1480_DUART_CMD_C               0x0010060450
#define A_BCM1480_DUART_RX_HOLD_C           0x0010060460
#define A_BCM1480_DUART_TX_HOLD_C           0x0010060470
#define A_BCM1480_DUART_OPCR_C              0x0010060480
#define A_BCM1480_DUART_AUX_CTRL_C          0x0010060490

#define A_BCM1480_DUART_MODE_REG_1_D        0x0010060500
#define A_BCM1480_DUART_MODE_REG_2_D        0x0010060510
#define A_BCM1480_DUART_STATUS_D            0x0010060520
#define A_BCM1480_DUART_CLK_SEL_D           0x0010060530
#define A_BCM1480_DUART_FULL_CTL_D          0x0010060540
#define A_BCM1480_DUART_CMD_D               0x0010060550
#define A_BCM1480_DUART_RX_HOLD_D           0x0010060560
#define A_BCM1480_DUART_TX_HOLD_D           0x0010060570
#define A_BCM1480_DUART_OPCR_D              0x0010060580
#define A_BCM1480_DUART_AUX_CTRL_D          0x0010060590

#define A_BCM1480_DUART_INPORT_CHNG_CD      0x0010060600
#define A_BCM1480_DUART_AUX_CTRL_CD         0x0010060610
#define A_BCM1480_DUART_ISR_C               0x0010060620
#define A_BCM1480_DUART_IMR_C               0x0010060630
#define A_BCM1480_DUART_ISR_D               0x0010060640
#define A_BCM1480_DUART_IMR_D               0x0010060650
#define A_BCM1480_DUART_OUT_PORT_CD         0x0010060660
#define A_BCM1480_DUART_OPCR_CD             0x0010060670
#define A_BCM1480_DUART_IN_PORT_CD          0x0010060680
#define A_BCM1480_DUART_ISR_CD              0x0010060690
#define A_BCM1480_DUART_IMR_CD              0x00100606A0
#define A_BCM1480_DUART_SET_OPR_CD          0x00100606B0
#define A_BCM1480_DUART_CLEAR_OPR_CD        0x00100606C0
#define A_BCM1480_DUART_INPORT_CHNG_C       0x00100606D0
#define A_BCM1480_DUART_INPORT_CHNG_D       0x00100606E0


/*  *********************************************************************
    * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16)
    ********************************************************************* */

#define A_BCM1480_IO_PCMCIA_CFG_B	0x0010061A58
#define A_BCM1480_IO_PCMCIA_STATUS_B	0x0010061A68

/*  *********************************************************************
    * GPIO Registers (Section 17)
    ********************************************************************* */

/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */

#define A_BCM1480_GPIO_INT_ADD_TYPE         0x0010061A78
#define R_BCM1480_GPIO_INT_ADD_TYPE         (-8)

#define A_GPIO_INT_ADD_TYPE	A_BCM1480_GPIO_INT_ADD_TYPE
#define R_GPIO_INT_ADD_TYPE	R_BCM1480_GPIO_INT_ADD_TYPE

/*  *********************************************************************
    * SMBus Registers (Section 18)
    ********************************************************************* */

/* No changes from BCM1250 */

/*  *********************************************************************
    * Timer Registers (Sections 4.6)
    ********************************************************************* */

/* BCM1480 has two additional watchdogs */

/* Watchdog timers */

#define A_BCM1480_SCD_WDOG_2                0x0010022050
#define A_BCM1480_SCD_WDOG_3                0x0010022150

#define BCM1480_SCD_NUM_WDOGS               4

#define A_BCM1480_SCD_WDOG_BASE(w)       (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))

#define A_BCM1480_SCD_WDOG_INIT_2       0x0010022050
#define A_BCM1480_SCD_WDOG_CNT_2        0x0010022058
#define A_BCM1480_SCD_WDOG_CFG_2        0x0010022060

#define A_BCM1480_SCD_WDOG_INIT_3       0x0010022150
#define A_BCM1480_SCD_WDOG_CNT_3        0x0010022158
#define A_BCM1480_SCD_WDOG_CFG_3        0x0010022160

/* BCM1480 has two additional compare registers */

#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT		A_SCD_ZBBUS_CYCLE_COUNT
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE       0x0010020C00
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0           A_SCD_ZBBUS_CYCLE_CP0
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1           A_SCD_ZBBUS_CYCLE_CP1
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2           0x0010020C10
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3           0x0010020C18

/*  *********************************************************************
    * System Control Registers (Section 4.2)
    ********************************************************************* */

/* Scratch register in different place */

#define A_BCM1480_SCD_SCRATCH	 	0x100200A0

/*  *********************************************************************
    * System Address Trap Registers (Section 4.9)
    ********************************************************************* */

/* No changes from BCM1250 */

/*  *********************************************************************
    * System Interrupt Mapper Registers (Sections 4.3-4.5)
    ********************************************************************* */

#define A_BCM1480_IMR_CPU0_BASE             0x0010020000
#define A_BCM1480_IMR_CPU1_BASE             0x0010022000
#define A_BCM1480_IMR_CPU2_BASE             0x0010024000
#define A_BCM1480_IMR_CPU3_BASE             0x0010026000
#define BCM1480_IMR_REGISTER_SPACING        0x2000
#define BCM1480_IMR_REGISTER_SPACING_SHIFT  13

#define A_BCM1480_IMR_MAPPER(cpu)       (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))

/* Most IMR registers are 128 bits, implemented as non-contiguous
   64-bit registers high (_H) and low (_L) */
#define BCM1480_IMR_HL_SPACING                  0x1000

#define R_BCM1480_IMR_INTERRUPT_DIAG_H          0x0010
#define R_BCM1480_IMR_LDT_INTERRUPT_H           0x0018
#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H       0x0020
#define R_BCM1480_IMR_INTERRUPT_MASK_H          0x0028
#define R_BCM1480_IMR_INTERRUPT_TRACE_H         0x0038
#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
#define R_BCM1480_IMR_LDT_INTERRUPT_SET         0x0048
#define R_BCM1480_IMR_MAILBOX_0_CPU             0x00C0
#define R_BCM1480_IMR_MAILBOX_0_SET_CPU         0x00C8
#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU         0x00D0
#define R_BCM1480_IMR_MAILBOX_1_CPU             0x00E0
#define R_BCM1480_IMR_MAILBOX_1_SET_CPU         0x00E8
#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU         0x00F0
#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H   0x0100
#define BCM1480_IMR_INTERRUPT_STATUS_COUNT      8
#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H      0x0200
#define BCM1480_IMR_INTERRUPT_MAP_COUNT         64

#define R_BCM1480_IMR_INTERRUPT_DIAG_L          0x1010
#define R_BCM1480_IMR_LDT_INTERRUPT_L           0x1018
#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L       0x1020
#define R_BCM1480_IMR_INTERRUPT_MASK_L          0x1028
#define R_BCM1480_IMR_INTERRUPT_TRACE_L         0x1038
#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L   0x1100
#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L      0x1200

#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE   0x0010028000
#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE   0x0010028100