path: root/include/asm-mips/pci/bridge.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
 * revision 1.76.
 *
 * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
 */
#ifndef _ASM_PCI_BRIDGE_H
#define _ASM_PCI_BRIDGE_H

#include <linux/types.h>
#include <linux/pci.h>
#include <asm/xtalk/xwidget.h>		/* generic widget header */
#include <asm/sn/types.h>

/* I/O page size */

#define IOPFNSHIFT		12	/* 4K per mapped page */

#define IOPGSIZE		(1 << IOPFNSHIFT)
#define IOPG(x)			((x) >> IOPFNSHIFT)
#define IOPGOFF(x)		((x) & (IOPGSIZE-1))

/* Bridge RAM sizes */

#define BRIDGE_ATE_RAM_SIZE	0x00000400	/* 1kB ATE RAM */

#define BRIDGE_CONFIG_BASE	0x20000
#define BRIDGE_CONFIG1_BASE	0x28000
#define BRIDGE_CONFIG_END	0x30000
#define BRIDGE_CONFIG_SLOT_SIZE 0x1000

#define BRIDGE_SSRAM_512K	0x00080000	/* 512kB */
#define BRIDGE_SSRAM_128K	0x00020000	/* 128kB */
#define BRIDGE_SSRAM_64K	0x00010000	/* 64kB */
#define BRIDGE_SSRAM_0K		0x00000000	/* 0kB */

/* ========================================================================
 *    Bridge address map
 */

#ifndef __ASSEMBLY__

/*
 * All accesses to bridge hardware registers must be done
 * using 32-bit loads and stores.
 */
typedef u32	bridgereg_t;

typedef u64	bridge_ate_t;

/* pointers to bridge ATEs
 * are always "pointer to volatile"
 */
typedef volatile bridge_ate_t  *bridge_ate_p;

/*
 * It is generally preferred that hardware registers on the bridge
 * are located from C code via this structure.
 *
 * Generated from Bridge spec dated 04oct95
 */

typedef volatile struct bridge_s {
	/* Local Registers			       0x000000-0x00FFFF */

	/* standard widget configuration	       0x000000-0x000057 */
	widget_cfg_t	    b_widget;			/* 0x000000 */

	/* helper fieldnames for accessing bridge widget */

#define b_wid_id			b_widget.w_id
#define b_wid_stat			b_widget.w_status
#define b_wid_err_upper			b_widget.w_err_upper_addr
#define b_wid_err_lower			b_widget.w_err_lower_addr
#define b_wid_control			b_widget.w_control
#define b_wid_req_timeout		b_widget.w_req_timeout
#define b_wid_int_upper			b_widget.w_intdest_upper_addr
#define b_wid_int_lower			b_widget.w_intdest_lower_addr
#define b_wid_err_cmdword		b_widget.w_err_cmd_word
#define b_wid_llp			b_widget.w_llp_cfg
#define b_wid_tflush			b_widget.w_tflush

	/* bridge-specific widget configuration	0x000058-0x00007F */
	bridgereg_t	    _pad_000058;
	bridgereg_t	    b_wid_aux_err;		/* 0x00005C */
	bridgereg_t	    _pad_000060;
	bridgereg_t	    b_wid_resp_upper;		/* 0x000064 */
	bridgereg_t	    _pad_000068;
	bridgereg_t	    b_wid_resp_lower;		/* 0x00006C */
	bridgereg_t	    _pad_000070;
	bridgereg_t	    b_wid_tst_pin_ctrl;		/* 0x000074 */
	bridgereg_t	_pad_000078[2];

	/* PMU & Map 0x000080-0x00008F */
	bridgereg_t	_pad_000080;
	bridgereg_t	b_dir_map;			/* 0x000084 */
	bridgereg_t	_pad_000088[2];

	/* SSRAM 0x000090-0x00009F */
	bridgereg_t	_pad_000090;
	bridgereg_t	b_ram_perr;			/* 0x000094 */
	bridgereg_t	_pad_000098[2];

	/* Arbitration 0x0000A0-0x0000AF */
	bridgereg_t	_pad_0000A0;
	bridgereg_t	b_arb;				/* 0x0000A4 */
	bridgereg_t	_pad_0000A8[2];

	/* Number In A Can 0x0000B0-0x0000BF */
	bridgereg_t	_pad_0000B0;
	bridgereg_t	b_nic;				/* 0x0000B4 */
	bridgereg_t	_pad_0000B8[2];

	/* PCI/GIO 0x0000C0-0x0000FF */
	bridgereg_t	_pad_0000C0;
	bridgereg_t	b_bus_timeout;			/* 0x0000C4 */
#define b_pci_bus_timeout b_bus_timeout

	bridgereg_t	_pad_0000C8;
	bridgereg_t	b_pci_cfg;			/* 0x0000CC */
	bridgereg_t	_pad_0000D0;
	bridgereg_t	b_pci_err_upper;		/* 0x0000D4 */
	bridgereg_t	_pad_0000D8;
	bridgereg_t	b_pci_err_lower;		/* 0x0000DC */
	bridgereg_t	_pad_0000E0[8];
#define b_gio_err_lower b_pci_err_lower
#define b_gio_err_upper b_pci_err_upper

	/* Interrupt 0x000100-0x0001FF */
	bridgereg_t	_pad_000100;
	bridgereg_t	b_int_status;			/* 0x000104 */
	bridgereg_t	_pad_000108;
	bridgereg_t	b_int_enable;			/* 0x00010C */
	bridgereg_t	_pad_000110;
	bridgereg_t	b_int_rst_stat;			/* 0x000114 */
	bridgereg_t	_pad_000118;
	bridgereg_t	b_int_mode;			/* 0x00011C */
	bridgereg_t	_pad_000120;
	bridgereg_t	b_int_device;			/* 0x000124 */
	bridgereg_t	_pad_000128;
	bridgereg_t	b_int_host_err;			/* 0x00012C */

	struct {
		bridgereg_t	__pad;			/* 0x0001{30,,,68} */
		bridgereg_t	addr;			/* 0x0001{34,,,6C} */
	} b_int_addr[8];				/* 0x000130 */

	bridgereg_t	_pad_000170[36];

	/* Device 0x000200-0x0003FF */
	struct {
		bridgereg_t	__pad;			/* 0x0002{00,,,38} */
		bridgereg_t	reg;			/* 0x0002{04,,,3C} */
	} b_device[8];					/* 0x000200 */

	struct {
		bridgereg_t	__pad;			/* 0x0002{40,,,78} */
		bridgereg_t	reg;			/* 0x0002{44,,,7C} */
	} b_wr_req_buf[8];				/* 0x000240 */

	struct {
		bridgereg_t	__pad;			/* 0x0002{80,,,88} */
		bridgereg_t	reg;			/* 0x0002{84,,,8C} */
	} b_rrb_map[2];					/* 0x000280 */
#define	b_even_resp	b_rrb_map[0].reg		/* 0x000284 */
#define	b_odd_resp	b_rrb_map[1].reg		/* 0x00028C */

	bridgereg_t	_pad_000290;
	bridgereg_t	b_resp_status;			/* 0x000294 */
	bridgereg_t	_pad_000298;
	bridgereg_t	b_resp_clear;			/* 0x00029C */

	bridgereg_t	_pad_0002A0[24];

	char		_pad_000300[0x10000 - 0x000300];

	/* Internal Address Translation Entry RAM 0x010000-0x0103FF */
	union {
		bridge_ate_t	wr;			/* write-only */
		struct {
			bridgereg_t	_p_pad;
			bridgereg_t	rd;		/* read-only */
		}			hi;
	}			    b_int_ate_ram[128];

	char	_pad_010400[0x11000 - 0x010400];

	/* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
	struct {
		bridgereg_t	_p_pad;
		bridgereg_t	rd;		/* read-only */
	} b_int_ate_ram_lo[128];

	char	_pad_011400[0x20000 - 0x011400];

	/* PCI Device Configuration Spaces 0x020000-0x027FFF */
	union {				/* make all access sizes available. */
		u8	c[0x1000 / 1];
		u16	s[0x1000 / 2];
		u32	l[0x1000 / 4];
		u64	d[0x1000 / 8];
		union {
			u8	c[0x100 / 1];
			u16	s[0x100 / 2];
			u32	l[0x100 / 4];
			u64	d[0x100 / 8];
		} f[8];
	} b_type0_cfg_dev[8];					/* 0x020000 */

    /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
	union {				/* make all access sizes available. */
		u8	c[0x1000 / 1];
		u16	s[0x1000 / 2];
		u32	l[0x1000 / 4];
		u64	d[0x1000 / 8];
	} b_type1_cfg;					/* 0x028000-0x029000 */

	char	_pad_029000[0x007000];			/* 0x029000-0x030000 */

	/* PCI Interrupt Acknowledge Cycle 0x030000 */
	union {
		u8	c[8 / 1];
		u16	s[8 / 2];
		u32	l[8 / 4];
		u64	d[8 / 8];
	} b_pci_iack;						/* 0x030000 */

	u8	_pad_030007[0x04fff8];			/* 0x030008-0x07FFFF */

	/* External Address Translation Entry RAM 0x080000-0x0FFFFF */
	bridge_ate_t    b_ext_ate_ram[0x10000];

	/* Reserved 0x100000-0x1FFFFF */
	char	_pad_100000[0x200000-0x100000];