aboutsummaryrefslogtreecommitdiff
path: root/include/asm-cris/arch-v32/hwregs/asm/eth_defs_asm.h
blob: c9f49864831b77361e41552cf5091cbb6260d8d5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
#ifndef __eth_defs_asm_h
#define __eth_defs_asm_h

/*
 * This file is autogenerated from
 *   file:           ../../inst/eth/rtl/eth_regs.r
 *     id:           eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
 *     last modfied: Mon Apr 11 16:07:03 2005
 *
 *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r
 *      id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */

#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif

#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif

#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif

#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif

#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
			 STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
                          ((inst) + offs + (index) * stride)
#endif

/* Register rw_ma0_lo, scope eth, type rw */
#define reg_eth_rw_ma0_lo___addr___lsb 0
#define reg_eth_rw_ma0_lo___addr___width 32
#define reg_eth_rw_ma0_lo_offset 0

/* Register rw_ma0_hi, scope eth, type rw */
#define reg_eth_rw_ma0_hi___addr___lsb 0
#define reg_eth_rw_ma0_hi___addr___width 16
#define reg_eth_rw_ma0_hi_offset 4

/* Register rw_ma1_lo, scope eth, type rw */
#define reg_eth_rw_ma1_lo___addr___lsb 0
#define reg_eth_rw_ma1_lo___addr___width 32
#define reg_eth_rw_ma1_lo_offset 8

/* Register rw_ma1_hi, scope eth, type rw */
#define reg_eth_rw_ma1_hi___addr___lsb 0
#define reg_eth_rw_ma1_hi___addr___width 16
#define reg_eth_rw_ma1_hi_offset 12

/* Register rw_ga_lo, scope eth, type rw */
#define reg_eth_rw_ga_lo___table___lsb 0
#define reg_eth_rw_ga_lo___table___width 32
#define reg_eth_rw_ga_lo_offset 16

/* Register rw_ga_hi, scope eth, type rw */
#define reg_eth_rw_ga_hi___table___lsb 0
#define reg_eth_rw_ga_hi___table___width 32
#define reg_eth_rw_ga_hi_offset 20

/* Register rw_gen_ctrl, scope eth, type rw */
#define reg_eth_rw_gen_ctrl___en___lsb 0
#define reg_eth_rw_gen_ctrl___en___width 1
#define reg_eth_rw_gen_ctrl___en___bit 0
#define reg_eth_rw_gen_ctrl___phy___lsb 1
#define reg_eth_rw_gen_ctrl___phy___width 2
#define reg_eth_rw_gen_ctrl___protocol___lsb 3
#define reg_eth_rw_gen_ctrl___protocol___width 1
#define reg_eth_rw_gen_ctrl___protocol___bit 3
#define reg_eth_rw_gen_ctrl___loopback___lsb 4
#define reg_eth_rw_gen_ctrl___loopback___width 1
#define reg_eth_rw_gen_ctrl___loopback___bit 4
#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5
#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1
#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5
#define reg_eth_rw_gen_ctrl_offset 24

/* Register rw_rec_ctrl, scope eth, type rw */
#define reg_eth_rw_rec_ctrl___ma0___lsb 0
#define reg_eth_rw_rec_ctrl___ma0___width 1
#define reg_eth_rw_rec_ctrl___ma0___bit 0
#define reg_eth_rw_rec_ctrl___ma1___lsb 1
#define reg_eth_rw_rec_ctrl___ma1___width 1
#define reg_eth_rw_rec_ctrl___ma1___bit 1
#define reg_eth_rw_rec_ctrl___individual___lsb 2
#define reg_eth_rw_rec_ctrl___individual___width 1
#define reg_eth_rw_rec_ctrl___individual___bit 2
#define reg_eth_rw_rec_ctrl___broadcast___lsb 3
#define reg_eth_rw_rec_ctrl___broadcast___width 1
#define reg_eth_rw_rec_ctrl___broadcast___bit 3
#define reg_eth_rw_rec_ctrl___undersize___lsb 4
#define reg_eth_rw_rec_ctrl___undersize___width 1
#define reg_eth_rw_rec_ctrl___undersize___bit 4
#define reg_eth_rw_rec_ctrl___oversize___lsb 5
#define reg_eth_rw_rec_ctrl___oversize___width 1
#define reg_eth_rw_rec_ctrl___oversize___bit 5
#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6
#define reg_eth_rw_rec_ctrl___bad_crc___width 1
#define reg_eth_rw_rec_ctrl___bad_crc___bit 6
#define reg_eth_rw_rec_ctrl___duplex___lsb 7
#define reg_eth_rw_rec_ctrl___duplex___width 1
#define reg_eth_rw_rec_ctrl___duplex___bit 7
#define reg_eth_rw_rec_ctrl___max_size___lsb 8
#define reg_eth_rw_rec_ctrl___max_size___width 1
#define reg_eth_rw_rec_ctrl___max_size___bit 8
#define reg_eth_rw_rec_ctrl_offset 28

/* Register rw_tr_ctrl, scope eth, type rw */
#define reg_eth_rw_tr_ctrl___crc___lsb 0
#define reg_eth_rw_tr_ctrl___crc___width 1
#define reg_eth_rw_tr_ctrl___crc___bit 0
#define reg_eth_rw_tr_ctrl___pad___lsb 1
#define reg_eth_rw_tr_ctrl___pad___width 1
#define reg_eth_rw_tr_ctrl___pad___bit 1
#define reg_eth_rw_tr_ctrl___retry___lsb 2
#define reg_eth_rw_tr_ctrl___retry___width 1
#define reg_eth_rw_tr_ctrl___retry___bit 2
#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3
#define reg_eth_rw_tr_ctrl___ignore_col___width 1
#define reg_eth_rw_tr_ctrl___ignore_col___bit 3
#define reg_eth_rw_tr_ctrl___cancel___lsb 4
#define reg_eth_rw_tr_ctrl___cancel___width 1
#define reg_eth_rw_tr_ctrl___cancel___bit 4
#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5
#define reg_eth_rw_tr_ctrl___hsh_delay___width 1
#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5
#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6
#define reg_eth_rw_tr_ctrl___ignore_crs___width 1
#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6
#define reg_eth_rw_tr_ctrl_offset 32

/* Register rw_clr_err, scope eth, type rw */
#define reg_eth_rw_clr_err___clr___lsb 0
#define reg_eth_rw_clr_err___clr___width 1
#define reg_eth_rw_clr_err___clr___bit 0
#define reg_eth_rw_clr_err_offset 36

/* Register rw_mgm_ctrl, scope eth, type rw */
#define reg_eth_rw_mgm_ctrl___mdio___lsb 0
#define reg_eth_rw_mgm_ctrl___mdio___width 1
#define reg_eth_rw_mgm_ctrl___mdio___bit 0
#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1
#define reg_eth_rw_mgm_ctrl___mdoe___width 1
#define reg_eth_rw_mgm_ctrl___mdoe___bit 1
#define reg_eth_rw_mgm_ctrl___mdc___lsb 2
#define reg_eth_rw_mgm_ctrl___mdc___width 1
#define reg_eth_rw_mgm_ctrl___mdc___bit 2
#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3
#define reg_eth_rw_mgm_ctrl___phyclk___width 1
#define reg_eth_rw_mgm_ctrl___phyclk___bit 3
#define reg_eth_rw_mgm_ctrl___txdata___lsb 4
#define reg_eth_rw_mgm_ctrl___txdata___width 4
#define reg_eth_rw_mgm_ctrl___txen___lsb 8
#define reg_eth_rw_mgm_ctrl___txen___width 1
#define reg_eth_rw_mgm_ctrl___txen___bit 8
#define reg_eth_rw_mgm_ctrl_offset 40

/* Register r_stat, scope eth, type r */
#define reg_eth_r_stat___mdio___lsb 0
#define reg_eth_r_stat___mdio___width 1
#define reg_eth_r_stat___mdio___bit 0
#define reg_eth_r_stat___exc_col___lsb 1
#define reg_eth_r_stat___exc_col___width 1
#define reg_eth_r_stat___exc_col___bit 1
#define reg_eth_r_stat___urun___lsb 2
#define reg_eth_r_stat___urun___width 1
#define reg_eth_r_stat___urun___bit 2
#define reg_eth_r_stat___phyclk___lsb 3
#define reg_eth_r_stat___phyclk___width 1
#define reg_eth_r_stat___phyclk___bit 3
#define reg_eth_r_stat___txdata___lsb 4
#define reg_eth_r_stat___txdata___width 4
#define reg_eth_r_stat___txen___lsb 8
#define reg_eth_r_stat___txen___width 1
#define reg_eth_r_stat___txen___bit 8
#define reg_eth_r_stat___col___lsb 9
#define reg_eth_r_stat___col___width 1
#define reg_eth_r_stat___col___bit 9
#define reg_eth_r_stat___crs___lsb 10
#define reg_eth_r_stat___crs___width 1
#define reg_eth_r_stat___crs___bit 10
#define reg_eth_r_stat___txclk___lsb 11
#define reg_eth_r_stat___txclk___width 1
#define reg_eth_r_stat___txclk___bit 11
#define reg_eth_r_stat___rxdata___lsb 12
#define reg_eth_r_stat___rxdata___width 4
#define reg_eth_r_stat___rxer___lsb 16
#define reg_eth_r_stat___rxer___width 1
#define reg_eth_r_stat___rxer___bit 16
#define reg_eth_r_stat___rxdv___lsb 17
#define reg_eth_r_stat___rxdv___width 1
#define reg_eth_r_stat___rxdv___bit 17
#define reg_eth_r_stat___rxclk___lsb 18
#define reg_eth_r_stat___rxclk___width 1
#define reg_eth_r_stat___rxclk___bit 18
#define reg_eth_r_stat_offset 44

/* Register rs_rec_cnt, scope eth, type rs */
#define reg_eth_rs_rec_cnt___crc_err___lsb 0
#define reg_eth_rs_rec_cnt___crc_err___width 8
#define reg_eth_rs_rec_cnt___align_err___lsb 8
#define reg_eth_rs_rec_cnt___align_err___width 8
#define reg_eth_rs_rec_cnt___oversize___lsb 16
#define reg_eth_rs_rec_cnt___oversize___width 8
#define reg_eth_rs_rec_cnt___congestion___lsb 24
#define reg_eth_rs_rec_cnt___congestion___width 8
#define reg_eth_rs_rec_cnt_offset 48

/* Register r_rec_cnt, scope eth, type r */
#define reg_eth_r_rec_cnt___crc_err___lsb 0
#define reg_eth_r_rec_cnt___crc_err___width 8
#define reg_eth_r_rec_cnt___align_err___lsb 8
#define reg_eth_r_rec_cnt___align_err___width 8
#define reg_eth_r_rec_cnt___oversize___lsb 16
#define reg_eth_r_rec_cnt___oversize___width 8
#define reg_eth_r_rec_cnt___congestion___lsb 24
#define reg_eth_r_rec_cnt___congestion___width 8
#define reg_eth_r_rec_cnt_offset 52

/* Register rs_tr_cnt, scope eth, type rs */
#define reg_eth_rs_tr_cnt___single_col___lsb 0
#define reg_eth_rs_tr_cnt___single_col___width 8
#define reg_eth_rs_tr_cnt___mult_col___lsb 8
#define reg_eth_rs_tr_cnt___mult_col___width 8
#define reg_eth_rs_tr_cnt___late_col___lsb 16
#define reg_eth_rs_tr_cnt___late_col___width 8
#define reg_eth_rs_tr_cnt___deferred___lsb 24
#define reg_eth_rs_tr_cnt___deferred___width 8
#define reg_eth_rs_tr_cnt_offset 56

/* Register r_tr_cnt, scope eth, type r */
#define reg_eth_r_tr_cnt___single_col___lsb 0
#define reg_eth_r_tr_cnt___single_col___width 8
#define reg_eth_r_tr_cnt___mult_col___lsb 8
#define reg_eth_r_tr_cnt___mult_col___width 8
#define reg_eth_r_tr_cnt___late_col___lsb 16
#define reg_eth_r_tr_cnt___late_col___width 8
#define reg_eth_r_tr_cnt___deferred___lsb 24
#define reg_eth_r_tr_cnt___deferred___width 8
#define reg_eth_r_tr_cnt_offset 60

/* Register rs_phy_cnt, scope eth, type rs */
#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0
#define reg_eth_rs_phy_cnt___carrier_loss___width 8
#define reg_eth_rs_phy_cnt___sqe_err___lsb 8
#define reg_eth_rs_phy_cnt___sqe_err___width 8
#define reg_eth_rs_phy_cnt_offset 64

/* Register r_phy_cnt, scope eth, type r */
#define reg_eth_r_phy_cnt___carrier_loss___lsb 0
#define reg_eth_r_phy_cnt___carrier_loss___width 8
#define reg_eth_r_phy_cnt___sqe_err___lsb 8
#define reg_eth_r_phy_cnt___sqe_err___width 8
#define reg_eth_r_phy_cnt_offset 68

/* Register rw_test_ctrl, scope eth, type rw */
#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0
#define reg_eth_rw_test_ctrl___snmp_inc___width 1
#define reg_eth_rw_test_ctrl___snmp_inc___bit 0
#define reg_eth_rw_test_ctrl___snmp___lsb 1
#define reg_eth_rw_test_ctrl___snmp___width 1
#define reg_eth_rw_test_ctrl___snmp___bit 1
#define reg_eth_rw_test_ctrl___backoff___lsb 2
#define reg_eth_rw_test_ctrl___backoff___width 1
#define reg_eth_rw_test_ctrl___backoff___bit 2
#define reg_eth_rw_test_ctrl_offset 72

/* Register rw_intr_mask, scope eth, type rw */
#define reg_eth_rw_intr_mask___crc___lsb 0
#define reg_eth_rw_intr_mask___crc___width 1
#define reg_eth_rw_intr_mask___crc___bit 0
#define reg_eth_rw_intr_mask___align___lsb 1
#define reg_eth_rw_intr_mask___align___width 1
#define reg_eth_rw_intr_mask___align___bit 1
#define reg_eth_rw_intr_mask___oversize___lsb 2
#define reg_eth_rw_intr_mask___oversize___width 1
#define reg_eth_rw_intr_mask___oversize___bit 2
#define reg_eth_rw_intr_mask___congestion___lsb 3
#define reg_eth_rw_intr_mask___congestion___width 1
#define reg_eth_rw_intr_mask___congestion___bit 3
#define reg_eth_rw_intr_mask___single_col___lsb 4
#define reg_eth_rw_intr_mask___single_col___width 1
#define reg_eth_rw_intr_mask___single_col___bit 4
#define reg_eth_rw_intr_mask___mult_col___lsb 5
#define reg_eth_rw_intr_mask___mult_col___width 1
#define reg_eth_rw_intr_mask___mult_col___bit 5
#define reg_eth_rw_intr_mask___late_col___lsb 6
#define reg_eth_rw_intr_mask___late_col___width 1
#define reg_eth_rw_intr_mask___late_col___bit 6
#define reg_eth_rw_intr_mask___deferred___lsb 7
#define reg_eth_rw_intr_mask___deferred___width 1
#define reg_eth_rw_intr_mask___deferred___bit 7
#define reg_eth_rw_intr_mask___carrier_loss___lsb 8
#define reg_eth_rw_intr_mask___carrier_loss___width 1
#define reg_eth_rw_intr_mask___carrier_loss___bit 8
#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9
#define reg_eth_rw_intr_mask___sqe_test_err___width 1
#define reg_eth_rw_intr_mask___sqe_test_err___bit 9
#define reg_eth_rw_intr_mask___orun___lsb 10
#define reg_eth_rw_intr_mask___orun___width 1
#define reg_eth_rw_intr_mask___orun___bit 10
#define reg_eth_rw_intr_mask___urun___lsb 11
#define reg_eth_rw_intr_mask___urun___width 1
#define reg_eth_rw_intr_mask___urun___bit 11
#define reg_eth_rw_intr_mask___excessive_col___lsb 12
#define reg_eth_rw_intr_mask___excessive_col___width 1
#define reg_eth_rw_intr_mask___excessive_col___bit 12
#define reg_eth_rw_intr_mask___mdio___lsb 13
#define reg_eth_rw_intr_mask___mdio___width 1
#define reg_eth_rw_intr_mask___mdio___bit 13
#define reg_eth_rw_intr_mask_offset 76

/* Register rw_ack_intr, scope eth, type rw */
#define reg_eth_rw_ack_intr___crc___lsb 0
#define reg_eth_rw_ack_intr___crc___width 1
#define reg_eth_rw_ack_intr___crc___bit 0
#define reg_eth_rw_ack_intr___align___lsb 1
#define reg_eth_rw_ack_intr___align___width 1
#define reg_eth_rw_ack_intr___align___bit 1
#define reg_eth_rw_ack_intr___oversize___lsb 2
#define reg_eth_rw_ack_intr___oversize___width 1
#define reg_eth_rw_ack_intr___oversize___bit 2
#define reg_eth_rw_ack_intr___congestion___lsb 3
#define reg_eth_rw_ack_intr___congestion___width 1
#define reg_eth_rw_ack_intr___congestion___bit 3
#define reg_eth_rw_ack_intr___single_col___lsb 4
#define reg_eth_rw_ack_intr___single_col___width 1
#define reg_eth_rw_ack_intr___single_col___bit 4
#define reg_eth_rw_ack_intr___mult_col___lsb 5
#define reg_eth_rw_ack_intr___mult_col___width 1
#define reg_eth_rw_ack_intr___mult_col___bit 5
#define reg_eth_rw_ack_intr___late_col___lsb 6
#define reg_eth_rw_ack_intr___late_col___width 1
#define reg_eth_rw_ack_intr___late_col___bit 6
#define reg_eth_rw_ack_intr___deferred___lsb 7
#define reg_eth_rw_ack_intr___deferred___width 1
#define reg_eth_rw_ack_intr___deferred___bit 7
#define reg_eth_rw_ack_intr___carrier_loss___lsb 8
#define reg_eth_rw_ack_intr___carrier_loss___width 1
#define reg_eth_rw_ack_intr___carrier_loss___bit 8
#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9
#define reg_eth_rw_ack_intr___sqe_test_err___width 1
#define reg_eth_rw_ack_intr___sqe_test_err___bit 9
#define reg_eth_rw_ack_intr___orun___lsb 10
#define reg_eth_rw_ack_intr___orun___width 1
#define reg_eth_rw_ack_intr___orun___bit 10
#define reg_eth_rw_ack_intr___urun___lsb 11
#define reg_eth_rw_ack_intr___urun___width 1
#define reg_eth_rw_ack_intr___urun___bit 11
#define reg_eth_rw_ack_intr___excessive_col___lsb 12
#define reg_eth_rw_ack_intr___excessive_col___width 1
#define reg_eth_rw_ack_intr___excessive_col___bit 12
#define reg_eth_rw_ack_intr___mdio___lsb 13
#define reg_eth_rw_ack_intr___mdio___width 1
#define reg_eth_rw_ack_intr___mdio___bit 13
#define reg_eth_rw_ack_intr_offset 80

/* Register r_intr, scope eth, type r */
#define reg_eth_r_intr___crc___lsb 0
#define reg_eth_r_intr___crc___width 1
#define reg_eth_r_intr___crc___bit 0
#define reg_eth_r_intr___align___lsb 1
#define reg_eth_r_intr___align___width 1
#define reg_eth_r_intr___align___bit 1
#define reg_eth_r_intr___oversize___lsb 2
#define reg_eth_r_intr___oversize___width 1
#define reg_eth_r_intr___oversize___bit 2
#define reg_eth_r_intr___congestion___lsb 3
#define reg_eth_r_intr___congestion___width 1
#define reg_eth_r_intr___congestion___bit 3
#define reg_eth_r_intr___single_col___lsb 4
#define reg_eth_r_intr___single_col___width 1
#define reg_eth_r_intr___single_col___bit 4
#define reg_eth_r_intr___mult_col___lsb 5
#define reg_eth_r_intr___mult_col___width 1
#define reg_eth_r_intr___mult_col___bit 5
#define reg_eth_r_intr___late_col___lsb 6
#define reg_eth_r_intr___late_col___width 1
#define reg_eth_r_intr___late_col___bit 6
#define reg_eth_r_intr___deferred___lsb 7
#define reg_eth_r_intr___deferred___width 1
#define reg_eth_r_intr___deferred___bit 7
#define reg_eth_r_intr___carrier_loss___lsb 8
#define reg_eth_r_intr___carrier_loss___width 1
#define reg_eth_r_intr___carrier_loss___bit 8
#define reg_eth_r_intr___sqe_test_err___lsb 9
#define reg_eth_r_intr___sqe_test_err___width 1
#define reg_eth_r_intr___sqe_test_err___bit 9
#define reg_eth_r_intr___orun___lsb 10
#define reg_eth_r_intr___orun___width 1
#define reg_eth_r_intr___orun___bit 10
#define reg_eth_r_intr___urun___lsb 11
#define reg_eth_r_intr___urun___width 1
#define reg_eth_r_intr___urun___bit 11
#define reg_eth_r_intr___excessive_col___lsb 12
#define reg_eth_r_intr___excessive_col___width 1
#define reg_eth_r_intr___excessive_col___bit 12
#define reg_eth_r_intr___mdio___lsb 13
#define reg_eth_r_intr___mdio___width 1
#define reg_eth_r_intr___mdio___bit 13
#define reg_eth_r_intr_offset 84

/* Register r_masked_intr, scope eth, type r */
#define reg_eth_r_masked_intr___crc___lsb 0
#define reg_eth_r_masked_intr___crc___width 1
#define reg_eth_r_masked_intr___crc___bit 0
#define reg_eth_r_masked_intr___align___lsb 1
#define reg_eth_r_masked_intr___align___width 1
#define reg_eth_r_masked_intr___align___bit 1
#define reg_eth_r_masked_intr___oversize___lsb 2
#define reg_eth_r_masked_intr___oversize___width 1
#define reg_eth_r_masked_intr___oversize___bit 2
#define reg_eth_r_masked_intr___congestion___lsb 3
#define reg_eth_r_masked_intr___congestion___width 1
#define reg_eth_r_masked_intr___congestion___bit 3
#define reg_eth_r_masked_intr___single_col___lsb 4
#define reg_eth_r_masked_intr___single_col___width 1
#define reg_eth_r_masked_intr___single_col___bit 4
#define reg_eth_r_masked_intr___mult_col___lsb 5
#define reg_eth_r_masked_intr___mult_col___width 1
#define reg_eth_r_masked_intr___mult_col___bit 5
#define reg_eth_r_masked_intr___late_col___lsb 6
#define reg_eth_r_masked_intr___late_col___width 1
#define reg_eth_r_masked_intr___late_col___bit 6
#define reg_eth_r_masked_intr___deferred___lsb 7
#define reg_eth_r_masked_intr___deferred___width 1
#define reg_eth_r_masked_intr___deferred___bit 7
#define reg_eth_r_masked_intr___carrier_loss___lsb 8
#define reg_eth_r_masked_intr___carrier_loss___width 1
#define reg_eth_r_masked_intr___carrier_loss___bit 8
#define reg_eth_r_masked_intr___sqe_test_err___lsb 9
#define reg_eth_r_masked_intr___sqe_test_err___width 1
#define reg_eth_r_masked_intr___sqe_test_err___bit 9
#define reg_eth_r_masked_intr___orun___lsb 10
#define reg_eth_r_masked_intr___orun___width 1
#define reg_eth_r_masked_intr___orun___bit 10
#define reg_eth_r_masked_intr___urun___lsb 11
#define reg_eth_r_masked_intr___urun___width 1
#define reg_eth_r_masked_intr___urun___bit 11
#define reg_eth_r_masked_intr___excessive_col___lsb 12
#define reg_eth_r_masked_intr___excessive_col___width 1
#define reg_eth_r_masked_intr___excessive_col___bit 12
#define reg_eth_r_masked_intr___mdio___lsb 13
#define reg_eth_r_masked_intr___mdio___width 1
#define reg_eth_r_masked_intr___mdio___bit 13
#define reg_eth_r_masked_intr_offset 88


/* Constants */
#define regk_eth_discard                          0x00000000
#define regk_eth_ether                            0x00000000
#define regk_eth_full                             0x00000001
#define regk_eth_half                             0x00000000
#define regk_eth_hsh                              0x00000001
#define regk_eth_mii                              0x00000001
#define regk_eth_mii_clk                          0x00000000
#define regk_eth_mii_rec                          0x00000002
#define regk_eth_no                               0x00000000
#define regk_eth_rec                              0x00000001
#define regk_eth_rw_ga_hi_default                 0x00000000
#define regk_eth_rw_ga_lo_default                 0x00000000
#define regk_eth_rw_gen_ctrl_default              0x00000000
#define regk_eth_rw_intr_mask_default             0x00000000
#define regk_eth_rw_ma0_hi_default                0x00000000
#define regk_eth_rw_ma0_lo_default                0x00000000
#define regk_eth_rw_ma1_hi_default                0x00000000
#define regk_eth_rw_ma1_lo_default                0x00000000
#define regk_eth_rw_mgm_ctrl_default              0x00000000
#define regk_eth_rw_test_ctrl_default             0x00000000
#define regk_eth_size1518                         0x00000000
#define regk_eth_size1522                         0x00000001
#define regk_eth_yes                              0x00000001
#endif /* __eth_defs_asm_h */