/*
* mfd.c: driver for High Speed UART device of Intel Medfield platform
*
* Refer pxa.c, 8250.c and some other drivers in drivers/serial/
*
* (C) Copyright 2009 Intel Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
/* Notes:
* 1. there should be 2 types of register access method, one for
* UART ports, the other for the general purpose registers
*
* 2. It used to have a Irda port, but was defeatured recently
*
* 3. Based on the info from HSU MAS, 0/1 channel are assigned to
* port0, 2/3 chan to port 1, 4/5 chan to port 3. Even number
* chan will be read, odd chan for write
*
* 4. HUS supports both the 64B and 16B FIFO version, but this driver
* will only use 64B version
*
* 5. In A0 stepping, UART will not support TX half empty flag, thus
* need add a #ifdef judgement
*
* 6. One more bug for A0, the loopback mode won't support AFC
* auto-flow control
*
* 7. HSU has some special FCR control bits, we add it to serial_reg.h
*
* 8. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always asserted,
* only when the HW is reset the DDCD and DDSR will be triggered
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/serial_reg.h>
#include <linux/circ_buf.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial_mfd.h>
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/debugfs.h>
#define MFD_HSU_A0_STEPPING 1
#define HSU_DMA_BUF_SIZE 2048
#define chan_readl(chan, offset) readl(chan->reg + offset)
#define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
#define mfd_readl(obj, offset) readl(obj->reg + offset)
#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
struct hsu_dma_buffer {
u8 *buf;
dma_addr_t dma_addr;
u32 dma_size;
u32 ofs;
};
struct hsu_dma_chan {
