path: root/drivers/pinctrl/pinctrl-pxa910.c

/*
 *  linux/drivers/pinctrl/pinmux-pxa910.c
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  publishhed by the Free Software Foundation.
 *
 *  Copyright (C) 2011, Marvell Technology Group Ltd.
 *
 *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
 *
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include "pinctrl-pxa3xx.h"

#define PXA910_DS_MASK		0x1800
#define PXA910_DS_SHIFT		11
#define PXA910_SLEEP_MASK	0x38
#define PXA910_SLEEP_SELECT	(1 << 9)
#define PXA910_SLEEP_DATA	(1 << 8)
#define PXA910_SLEEP_DIR	(1 << 7)

#define MFPR_910(a, r, f0, f1, f2, f3, f4, f5, f6, f7)		\
	{							\
		.name = #a,					\
		.pin = a,					\
		.mfpr = r,					\
		.func = {					\
			PXA910_MUX_##f0,			\
			PXA910_MUX_##f1,			\
			PXA910_MUX_##f2,			\
			PXA910_MUX_##f3,			\
			PXA910_MUX_##f4,			\
			PXA910_MUX_##f5,			\
			PXA910_MUX_##f6,			\
			PXA910_MUX_##f7,			\
		},						\
	}

#define GRP_910(a, m, p)		\
	{ .name = a, .mux = PXA910_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }

/* 170 pins */
enum pxa910_pin_list {
	/* 0~127: GPIO0~GPIO127 */
	ND_IO15 = 128,
	ND_IO14,
	ND_IO13, /* 130 */
	ND_IO12,
	ND_IO11,
	ND_IO10,
	ND_IO9,
	ND_IO8,
	ND_IO7,
	ND_IO6,
	ND_IO5,
	ND_IO4,
	ND_IO3, /* 140 */
	ND_IO2,
	ND_IO1,
	ND_IO0,
	ND_NCS0,
	ND_NCS1,
	SM_NCS0,
	SM_NCS1,
	ND_NWE,
	ND_NRE,
	ND_CLE, /* 150 */
	ND_ALE,
	SM_SCLK,
	ND_RDY0,
	SM_ADV,
	ND_RDY1,
	SM_ADVMUX,
	SM_RDY,
	MMC1_DAT7,
	MMC1_DAT6,
	MMC1_DAT5, /* 160 */
	MMC1_DAT4,
	MMC1_DAT3,
	MMC1_DAT2,
	MMC1_DAT1,
	MMC1_DAT0,
	MMC1_CMD,
	MMC1_CLK,
	MMC1_CD,
	VCXO_OUT,
};

enum pxa910_mux {
	/* PXA3xx_MUX_GPIO = 0 (predefined in pinctrl-pxa3xx.h) */
	PXA910_MUX_GPIO = 0,
	PXA910_MUX_NAND,
	PXA910_MUX_USIM2,
	PXA910_MUX_EXT_DMA,
	PXA910_MUX_EXT_INT,
	PXA910_MUX_MMC1,
	PXA910_MUX_MMC2,
	PXA910_MUX_MMC3,
	PXA910_MUX_SM_INT,
	PXA910_MUX_PRI_JTAG,
	PXA910_MUX_SEC1_JTAG,
	PXA910_MUX_SEC2_JTAG,
	PXA910_MUX_RESET,	/* SLAVE RESET OUT */
	PXA910_MUX_CLK_REQ,
	PXA910_MUX_VCXO_REQ,
	PXA910_MUX_VCXO_OUT,
	PXA910_MUX_VCXO_REQ2,
	PXA910_MUX_VCXO_OUT2,
	PXA910_MUX_SPI,
	PXA910_MUX_SPI2,
	PXA910_MUX_GSSP,
	PXA910_MUX_SSP0,
	PXA910_MUX_SSP1,
	PXA910_MUX_SSP2,
	PXA910_MUX_DSSP2,
	PXA910_MUX_DSSP3,
	PXA910_MUX_UART0,
	PXA910_MUX_UART1,
	PXA910_MUX_UART2,
	PXA910_MUX_TWSI,
	PXA910_MUX_CCIC,
	PXA910_MUX_PWM0,
	PXA910_MUX_PWM1,
	PXA910_MUX_PWM2,
	PXA910_MUX_PWM3,
	PXA910_MUX_HSL,
	PXA910_MUX_ONE_WIRE,
	PXA910_MUX_LCD,
	PXA910_MUX_DAC_ST23,
	PXA910_MUX_ULPI,
	PXA910_MUX_TB,
	PXA910_MUX_KP_MK,
	PXA910_MUX_KP_DK,
	PXA910_MUX_TCU_GPOA,
	PXA910_MUX_TCU_GPOB,
	PXA910_MUX_ROT,
	PXA910_MUX_TDS,
	PXA910_MUX_32K_CLK, /* 32KHz CLK OUT */
	PXA910_MUX_MN_CLK, /* MN CLK OUT */
	PXA910_MUX_SMC,
	PXA910_MUX_SM_ADDR18,
	PXA910_MUX_SM_ADDR19,
	PXA910_MUX_SM_ADDR20,
	PXA910_MUX_NONE = 0xffff,
};


static struct pinctrl_pin_desc pxa910_pads[] = {
	PINCTRL_PIN(GPIO0, "GPIO0"),
	PINCTRL_PIN(GPIO1, "GPIO1"),
	PINCTRL_PIN(GPIO2, "GPIO2"),
	PINCTRL_PIN(GPIO3, "GPIO3"),
	PINCTRL_PIN(GPIO4, "GPIO4"),
	PINCTRL_PIN(GPIO5, "GPIO5"),
	PINCTRL_PIN(GPIO6, "GPIO6"),
	PINCTRL_PIN(GPIO7, "GPIO7"),
	PINCTRL_PIN(GPIO8, "GPIO8"),
	PINCTRL_PIN(GPIO9, "GPIO9"),
	PINCTRL_PIN(GPIO10, "GPIO10"),
	PINCTRL_PIN(GPIO11, "GPIO11"),
	PINCTRL_PIN(GPIO12, "GPIO12"),
	PINCTRL_PIN(GPIO13, "GPIO13"),
	PINCTRL_PIN(GPIO14, "GPIO14"),
	PINCTRL_PIN(GPIO15, "GPIO15"),
	PINCTRL_PIN(GPIO16, "GPIO16"),
	PINCTRL_PIN(GPIO17, "GPIO17"),
	PINCTRL_PIN(GPIO18, "GPIO18"),
	PINCTRL_PIN(GPIO19, "GPIO19"),
	PINCTRL_PIN(GPIO20, "GPIO20"),
	PINCTRL_PIN(GPIO21, "GPIO21"),
	PINCTRL_PIN(GPIO22, "GPIO22"),
	PINCTRL_PIN(GPIO23, "GPIO23"),
	PINCTRL_PIN(GPIO24, "GPIO24"),
	PINCTRL_PIN(GPIO25, "GPIO25"),
	PINCTRL_PIN(GPIO26, "GPIO26"),
	PINCTRL_PIN(GPIO27, "GPIO27"),
	PINCTRL_PIN(GPIO28, "GPIO28"),
	PINCTRL_PIN(GPIO29, "GPIO29"),
	PINCTRL_PIN(GPIO30, "GPIO30"),
	PINCTRL_PIN(GPIO31, "GPIO31"),
	PINCTRL_PIN(GPIO32, "GPIO32"),
	PINCTRL_PIN(GPIO33, "GPIO33"),
	PINCTRL_PIN(GPIO34, "GPIO34"),
	PINCTRL_PIN(GPIO35, "GPIO35"),
	PINCTRL_PIN(GPIO36, "GPIO36"),
	PINCTRL_PIN(GPIO37, "GPIO37"),
	PINCTRL_PIN(GPIO38, "GPIO38"),
	PINCTRL_PIN(GPIO39, "GPIO39"),
	PINCTRL_PIN(GPIO40, "GPIO40"),
	PINCTRL_PIN(GPIO41, "GPIO41"),
	PINCTRL_PIN(GPIO42, "GPIO42"),
	PINCTRL_PIN(GPIO43, "GPIO43"),
	PINCTRL_PIN(GPIO44, "GPIO44"),
	PINCTRL_PIN(GPIO45, "GPIO45"),
	PINCTRL_PIN(GPIO46, "GPIO46"),
	PINCTRL_PIN(GPIO47,