path: root/drivers/net/wireless/zd1211rw/zd_chip.h

/* ZD1211 USB-WLAN driver for Linux
 *
 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef _ZD_CHIP_H
#define _ZD_CHIP_H

#include "zd_rf.h"
#include "zd_usb.h"

/* Header for the Media Access Controller (MAC) and the Baseband Processor
 * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and
 * adds a processor for handling the USB protocol.
 */

/* Address space */
enum {
	/* CONTROL REGISTERS */
	CR_START			= 0x9000,


	/* FIRMWARE */
	FW_START			= 0xee00,


	/* EEPROM */
	E2P_START			= 0xf800,
	E2P_LEN				= 0x800,

	/* EEPROM layout */
	E2P_LOAD_CODE_LEN		= 0xe,		/* base 0xf800 */
	E2P_LOAD_VECT_LEN		= 0x9,		/* base 0xf80e */
	/* E2P_DATA indexes into this */
	E2P_DATA_LEN			= 0x7e,		/* base 0xf817 */
	E2P_BOOT_CODE_LEN		= 0x760,	/* base 0xf895 */
	E2P_INTR_VECT_LEN		= 0xb,		/* base 0xfff5 */

	/* Some precomputed offsets into the EEPROM */
	E2P_DATA_OFFSET			= E2P_LOAD_CODE_LEN + E2P_LOAD_VECT_LEN,
	E2P_BOOT_CODE_OFFSET		= E2P_DATA_OFFSET + E2P_DATA_LEN,
};

#define CTL_REG(offset) ((zd_addr_t)(CR_START + (offset)))
#define E2P_DATA(offset) ((zd_addr_t)(E2P_START + E2P_DATA_OFFSET + (offset)))
#define FWRAW_DATA(offset) ((zd_addr_t)(FW_START + (offset)))

/* 8-bit hardware registers */
#define ZD_CR0   CTL_REG(0x0000)
#define ZD_CR1   CTL_REG(0x0004)
#define ZD_CR2   CTL_REG(0x0008)
#define ZD_CR3   CTL_REG(0x000C)

#define ZD_CR5   CTL_REG(0x0010)
/*	bit 5: if set short preamble used
 *	bit 6: filter band - Japan channel 14 on, else off
 */
#define ZD_CR6   CTL_REG(0x0014)
#define ZD_CR7   CTL_REG(0x0018)
#define ZD_CR8   CTL_REG(0x001C)

#define ZD_CR4   CTL_REG(0x0020)

#define ZD_CR9   CTL_REG(0x0024)
/*	bit 2: antenna switch (together with ZD_CR10) */
#define ZD_CR10  CTL_REG(0x0028)
/*	bit 1: antenna switch (together with ZD_CR9)
 *	RF2959 controls with ZD_CR11 radion on and off
 */
#define ZD_CR11  CTL_REG(0x002C)
/*	bit 6:  TX power control for OFDM
 *	RF2959 controls with ZD_CR10 radio on and off
 */
#define ZD_CR12  CTL_REG(0x0030)
#define ZD_CR13  CTL_REG(0x0034)
#define ZD_CR14  CTL_REG(0x0038)
#define ZD_CR15  CTL_REG(0x003C)
#define ZD_CR16  CTL_REG(0x0040)
#define ZD_CR17  CTL_REG(0x0044)
#define ZD_CR18  CTL_REG(0x0048)
#define ZD_CR19  CTL_REG(0x004C)
#define ZD_CR20  CTL_REG(0x0050)
#define ZD_CR21  CTL_REG(0x0054)
#define ZD_CR22  CTL_REG(0x0058)
#define ZD_CR23  CTL_REG(0x005C)
#define ZD_CR24  CTL_REG(0x0060)	/* CCA threshold */
#define ZD_CR25  CTL_REG(0x0064)
#define ZD_CR26  CTL_REG(0x0068)
#define ZD_CR27  CTL_REG(0x006C)
#define ZD_CR28  CTL_REG(0x0070)
#define ZD_CR29  CTL_REG(0x0074)
#define ZD_CR30  CTL_REG(0x0078)
#define ZD_CR31  CTL_REG(0x007C)	/* TX power control for RF in
					 * CCK mode
					 */
#define ZD_CR32  CTL_REG(0x0080)
#define ZD_CR33  CTL_REG(0x0084)
#define ZD_CR34  CTL_REG(0x0088)
#define ZD_CR35  CTL_REG(0x008C)
#define ZD_CR36  CTL_REG(0x0090)
#define ZD_CR37  CTL_REG(0x0094)
#define ZD_CR38  CTL_REG(0x0098)
#define ZD_CR39  CTL_REG(0x009C)
#define ZD_CR40  CTL_REG(0x00A0)
#define ZD_CR41  CTL_REG(0x00A4)
#define ZD_CR42  CTL_REG(0x00A8)
#define ZD_CR43  CTL_REG(0x00AC)
#define ZD_CR44  CTL_REG(0x00B0)
#define ZD_CR45  CTL_REG(0x00B4)
#define ZD_CR46  CTL_REG(0x00B8)
#define ZD_CR47  CTL_REG(0x00BC)	/* CCK baseband gain
					 * (patch value might be in EEPROM)
					 */
#define ZD_CR48  CTL_REG(0x00C0)
#define ZD_CR49  CTL_REG(0x00C4)
#define ZD_CR50  CTL_REG(0x00C8)
#define ZD_CR51  CTL_REG(0x00CC)	/* TX power control for RF in
					 * 6-36M modes
					 */
#define ZD_CR52  CTL_REG(0x00D0)	/* TX power control for RF in
					 * 48M mode
					 */
#define ZD_CR53  CTL_REG(0x00D4)	/* TX power control for RF in
					 * 54M mode
					 */
#define ZD_CR54  CTL_REG(0x00D8)
#define ZD_CR55  CTL_REG(0x00DC)
#define ZD_CR56  CTL_REG(0x00E0)
#define ZD_CR57  CTL_REG(0x00E4)
#define ZD_CR58  CTL_REG(0x00E8)
#define ZD_CR59  CTL_REG(0x00EC)
#define ZD_CR60  CTL_REG(0x00F0)
#define ZD_CR61  CTL_REG(0x00F4)
#define ZD_CR62  CTL_REG(0x00F8)
#define ZD_CR63  CTL_REG(0x00FC)
#define ZD_CR64  CTL_REG(0x0100)
#define ZD_CR65  CTL_REG(0x0104) /* OFDM 54M calibration */
#define ZD_CR66  CTL_REG(0x0108) /* OFDM 48M calibration */
#define ZD_CR67  CTL_REG(0x010C) /* OFDM 36M calibration */
#define ZD_CR68  CTL_REG(0x0110) /* CCK calibration */
#define ZD_CR69  CTL_REG(0x0114)
#define ZD_CR70  CTL_REG(0x0118)
#define ZD_CR71  CTL_REG(0x011C)
#define ZD_CR72  CTL_REG(0x0120)
#define ZD_CR73  CTL_REG(0x0124)
#define ZD_CR74  CTL_REG(0x0128)
#define ZD_CR75  CTL_REG(0x012C)
#define ZD_CR76  CTL_REG(0x0130)
#define ZD_CR77  CTL_REG(0x0134)
#define ZD_CR78  CTL_REG(0x0138)
#define ZD_CR79  CTL_REG(0x013C)
#define ZD_CR80  CTL_REG(0x0140)
#define ZD_CR81  CTL_REG(0x0144)
#define ZD_CR82  CTL_REG(0x0148)
#define ZD_CR83  CTL_REG(0x014C)
#define ZD_CR84  CTL_REG(0x0150)
#define ZD_CR85  CTL_REG(0x0154)
#define ZD_CR86  CTL_REG(0x0158)
#define ZD_CR87  CTL_REG(0x015C)
#define ZD_CR88  CTL_REG(0x0160)
#define ZD_CR89  CTL_REG(0x0164)
#define ZD_CR90  CTL_REG(0x0168)
#define ZD_CR91  CTL_REG(0x016C)
#define ZD_CR92  CTL_REG(0x0170)
#define ZD_CR93  CTL_REG(0x0174)
#define ZD_CR94  CTL_REG(0x0178)
#define ZD_CR95  CTL_REG(0x017C)
#define ZD_CR96  CTL_REG(0x0180)
#define ZD_CR97  CTL_REG(0x0184)
#define ZD_CR98  CTL_REG(0x0188)
#define ZD_CR99  CTL_REG(0x018C)
#define ZD_CR100 CTL_REG(0x0190)
#define ZD_CR101 CTL_REG(0x0194)
#define ZD_CR102 CTL_REG(0x0198)
#define ZD_CR103 CTL_REG(0x019C)
#define ZD_CR104 CTL_REG(0x01A0)
#define ZD_CR105 CTL_REG(0x01A4)
#define ZD_CR106 CTL_REG(0x01A8)
#define ZD_CR107 CTL_REG(0x01AC)
#define ZD_CR108 CTL_REG(0x01B0)
#define ZD_CR109 CTL_REG(0x01B4)
#define ZD_CR110 CTL_REG(0x01B8)
#define ZD_CR111 CTL_REG(0x01BC)
#define ZD_CR112 CTL_REG(0x01C0)
#define ZD_CR113 CTL_REG(0x01C4)
#define ZD_CR114 CTL_REG(0x01C8)
#define ZD_CR115 CTL_REG(0x01CC)
#define ZD_CR116 CTL_REG(0x01D0)
#define ZD_CR117 CTL_REG(0x01D4)
#define ZD_CR118 CTL_REG(0x01D8)
#define ZD_CR119 CTL_REG(0x01DC)
#define ZD_CR120 CTL_REG(0x01E0)
#define ZD_CR121 CTL_REG(0x01E4)
#define ZD_CR122 CTL_REG(0x01E8)
#define ZD_CR123 CTL_REG(0x01EC)
#define ZD_CR124 CTL_REG(0x01F0)
#define ZD_CR125 CTL_REG(0x01F4)
#define ZD_CR126 CTL_REG(0x01F8)
#define ZD_CR127 CTL_REG(0x01FC)
#define ZD_CR128 CTL_REG(0x0200)
#define ZD_CR129 CTL_REG(0x0204)
#define ZD_CR130 CTL_REG(0x0208)
#define ZD_CR131 CTL_REG(0x020C)
#define ZD_CR132 CTL_REG(0x0210)
#define ZD_CR133 CTL_REG(0x0214)
#define ZD_CR134 CTL_REG(0x0218)
#define ZD_CR135 CTL_REG(0x021C)
#define ZD_CR136 CTL_REG(0x0220)
#define ZD_CR137 CTL_REG(0x0224)
#define ZD_CR138 CTL_REG(0x0228)
#define ZD_CR139 CTL_REG(0x022C)
#define ZD_CR140 CTL_REG(0x0230)
#define ZD_CR141 CTL_REG(0x0234)
#define ZD_CR142 CTL_REG(0x0238)
#define ZD_CR143 CTL_REG(0x023C)
#define ZD_CR144 CTL_REG(0x0240)
#define ZD_CR145 CTL_REG(0x0244)
#define ZD_CR146 CTL_REG(0x0248)
#define ZD_CR147 CTL_REG(0x024C)
#define ZD_CR148 CTL_REG(0x0250)
#define ZD_CR149 CTL_REG(0x0254)
#define ZD_CR150 CTL_REG(0x0258)
#define ZD_CR151 CTL_REG(0x025C)
#define ZD_CR152 CTL_REG(0x0260)
#define ZD_CR153 CTL_REG(0x0264)
#define ZD_CR154 CTL_REG(0x0268)
#define ZD_CR155 CTL_REG(0x026C)
#define ZD_CR156 CTL_REG(0x0270)
#define ZD_CR157 CTL_REG(0x0274)
#define ZD_CR158 CTL_REG(0x0278)
#define ZD_CR159 CTL_REG(0x027C)
#define ZD_CR160 CTL_REG(0x0280)
#define ZD_CR161 CTL_REG(0x0284)
#define ZD_CR162 CTL_REG(0x0288)
#define ZD_CR163 CTL_REG(0x028C)
#define ZD_CR164 CTL_REG(0x0290)
#define ZD_CR165 CTL_REG(0x0294)
#define ZD_CR166 CTL_REG(0x0298)
#define ZD_CR167 CTL_REG(0x029C)
#define ZD_CR168 CTL_REG(0x02A0)
#define ZD_CR169 CTL_REG(0x02A4)
#define ZD_CR170 CTL_REG(0x02A8)
#define ZD_CR171 CTL_REG(0x02AC)
#define ZD_CR172 CTL_REG(0x02B0)
#define ZD_CR173 CTL_REG(0x02B4)
#define ZD_CR174 CTL_REG(0x02B8)
#define ZD_CR175 CTL_REG(0x02BC)
#define ZD_CR176 CTL_REG(0x02C0)
#define ZD_CR177 CTL_REG(0x02C4)
#define ZD_CR178 CTL_REG(0x02C8)
#define ZD_CR179 CTL_REG(0x02CC)
#define ZD_CR180 CTL_REG(0x02D0)
#define ZD_CR181 CTL_REG(0x02D4)
#define ZD_CR182 CTL_REG(0x02D8)
#define ZD_CR183 CTL_REG(0x02DC)
#define ZD_CR184 CTL_REG(0x02E0)
#define ZD_CR185 CTL_REG(0x02E4)
#define ZD_CR186 CTL_REG(0x02E8)
#define ZD_CR187 CTL_REG(0x02EC)
#define ZD_CR188 CTL_REG(0x02F0)
#define ZD_CR189 CTL_REG(0x02F4)
#define ZD_CR190 CTL_REG(0x02F8)
#define ZD_CR191 CTL_REG(0x02FC)
#define ZD_CR192 CTL_REG(0x0300)
#define ZD_CR193 CTL_REG(0x0304)
#define ZD_CR194 CTL_REG(0x0308)
#define ZD_CR195 CTL_REG(0x030C)
#define ZD_CR196 CTL_REG(0x0310)
#define ZD_CR197 CTL_REG(0x0314)
#define ZD_CR198 CTL_REG(0x0318)
#define ZD_CR199 CTL_REG(0x031C)
#define ZD_CR200 CTL_REG(0x0320)
#define ZD_CR201 CTL_REG(0x0324)
#define ZD_CR202 CTL_REG(0x0328)
#define ZD_CR203 CTL_REG(0x032C)	/* I2C bus template value & flash
					 * control
					 */
#define ZD_CR204 CTL_REG(0x0330)
#define ZD_CR205 CTL_REG(0x0334)
#define ZD_CR206 CTL_REG(0x0338)
#define ZD_CR207 CTL_REG(0x033C)
#define ZD_CR208 CTL_REG(0x0340)
#define ZD_CR209 CTL_REG(0x0344)
#define ZD_CR210 CTL_REG(0x0348)
#define ZD_CR211 CTL_REG(0x034C)
#define ZD_CR212 CTL_REG(0x0350)
#define ZD_CR213 CTL_REG(0x0354)
#define ZD_CR214 CTL_REG(0x0358)
#define ZD_CR215 CTL_REG(0x035C)
#define ZD_CR216 CTL_REG(0x0360)
#define ZD_CR217 CTL_REG(0x0364)
#define ZD_CR218 CTL_REG(0x0368)
#define ZD_CR219 CTL_REG(0x036C)
#define ZD_CR220 CTL_REG(0x0370)
#define ZD_CR221 CTL_REG(0x0374)
#define ZD_CR222 CTL_REG(0x0378)
#define ZD_CR223 CTL_REG(0x037C)
#define ZD_CR224 CTL_REG(0x0380)
#define ZD_CR225 CTL_REG(0x0384)
#define ZD_CR226 CTL_REG(0x0388)
#define ZD_CR227 CTL_REG(0x038C)
#define ZD_CR228 CTL_REG(0x0390)
#define ZD_CR229 CTL_REG(0x0394)
#define ZD_CR230 CTL_REG(0x0398)
#define ZD_CR231 CTL_REG(0x039C)
#define ZD_CR232 CTL_REG(0x03A0)
#define ZD_CR233 CTL_REG(0x03A4)
#define ZD_CR234 CTL_REG(0x03A8)
#define ZD_CR235 CTL_REG(0x03AC)
#define ZD_CR236 CTL_REG(0x03B0)

#define ZD_CR240 CTL_REG(0x03C0)
/*             bit 7: host-controlled RF register writes
 * ZD_CR241-ZD_CR245: for hardware controlled writing of RF bits, not needed for
 *                    USB
 */
#define ZD_CR241 CTL_REG(0x03C4)
#define ZD_CR242 CTL_REG(0x03C8)
#define ZD_CR243 CTL_REG(0x03CC)
#define ZD_CR244 CTL_REG(0x03D0)
#define ZD_CR245 CTL_REG(0x03D4)

#define ZD_CR251 CTL_REG(0x03EC)	/* only used for activation and
					 * deactivation of Airoha RFs AL2230
					 * and AL7230B
					 */
#define ZD_CR252 CTL_REG(0x03F0)
#define ZD_CR253 CTL_REG(0x03F4)
#define ZD_CR254 CTL_REG(0x03F8)
#define ZD_CR255 CTL_REG(0x03FC)

#define CR_MAX_PHY_REG 255

/* Taken from the ZYDAS driver, not all of them are relevant for the ZD1211
 * driver.
 */

#define CR_RF_IF_CLK			CTL_REG(0x0400)
#define CR_RF_IF_DATA			CTL_REG(0x0404)
#define CR_PE1_PE2			CTL_REG(0x0408)
#define CR_PE2_DLY			CTL_REG(0x040C)
#define CR_LE1				CTL_REG(0x0410)
#define CR_LE2				CTL_REG(0x0414)
/* Seems to enable/disable GPI (General Purpose IO?) */
#define CR_GPI_EN			CTL_REG(0x0418)
#define CR_RADIO_PD			CTL_REG(0x042C)
#define CR_RF2948_PD			CTL_REG(0x042C)
#define CR_ENABLE_PS_MANUAL_AGC		CTL_REG(0x043C)
#define CR_CONFIG_PHILIPS		CTL_REG(0x0440)
#define CR_SA2400_SER_AP		CTL_REG(0x0444)
#define CR_I2C_WRITE			CTL_REG(0x0444)
#define CR_SA2400_SER_RP		CTL_REG(0x0448)
#define CR_RADIO_PE			CTL_REG(0x0458)
#define CR_RST_BUS_MASTER		CTL_REG(0x045C)
#define CR_RFCFG			CTL_REG(0x0464)
#define CR_HSTSCHG			CTL_REG(0x046C)
#define CR_PHY_ON			CTL_REG(0x0474)
#define CR_RX_DELAY			CTL_REG(0x0478)
#define CR_RX_PE_DELAY			CTL_REG(0x047C)
#define CR_GPIO_1			CTL_REG(0x0490)
#define CR_GPIO_2			CTL_REG(0x0494)
#def