/*
Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt61pci
Abstract: Data structures and registers for the rt61pci module.
Supported chipsets: RT2561, RT2561s, RT2661.
*/
#ifndef RT61PCI_H
#define RT61PCI_H
/*
* RF chip defines.
*/
#define RF5225 0x0001
#define RF5325 0x0002
#define RF2527 0x0003
#define RF2529 0x0004
/*
* Signal information.
* Default offset is required for RSSI <-> dBm conversion.
*/
#define DEFAULT_RSSI_OFFSET 120
/*
* Register layout information.
*/
#define CSR_REG_BASE 0x3000
#define CSR_REG_SIZE 0x04b0
#define EEPROM_BASE 0x0000
#define EEPROM_SIZE 0x0100
#define BBP_BASE 0x0000
#define BBP_SIZE 0x0080
#define RF_BASE 0x0004
#define RF_SIZE 0x0010
/*
* Number of TX queues.
*/
#define NUM_TX_QUEUES 4
/*
* PCI registers.
*/
/*
* HOST_CMD_CSR: For HOST to interrupt embedded processor
*/
#define HOST_CMD_CSR 0x0008
#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
#define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
/*
* MCU_CNTL_CSR
* SELECT_BANK: Select 8051 program bank.
* RESET: Enable 8051 reset state.
* READY: Ready state for 8051.
*/
#define MCU_CNTL_CSR 0x000c
#define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
#define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
#define MCU_CNTL_CSR_READY FIELD32(0x00000004)
/*
* SOFT_RESET_CSR
* FORCE_CLOCK_ON: Host force MAC clock ON
*/
#define SOFT_RESET_CSR 0x0010
#define SOFT_RESET_CSR_FORCE_CLOCK_ON FIELD32(0x00000002)
/*
* MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
*/
#define MCU_INT_SOURCE_CSR 0x0014
#define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
#define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
#define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
#define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
#define MCU_INT_SOURCE_CS
