path: root/drivers/net/wireless/rt2x00/rt2400pci.h

/*
	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
	<http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the
	Free Software Foundation, Inc.,
	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
	Module: rt2400pci
	Abstract: Data structures and registers for the rt2400pci module.
	Supported chipsets: RT2460.
 */

#ifndef RT2400PCI_H
#define RT2400PCI_H

/*
 * RF chip defines.
 */
#define RF2420				0x0000
#define RF2421				0x0001

/*
 * Signal information.
 * Default offset is required for RSSI <-> dBm conversion.
 */
#define DEFAULT_RSSI_OFFSET		100

/*
 * Register layout information.
 */
#define CSR_REG_BASE			0x0000
#define CSR_REG_SIZE			0x014c
#define EEPROM_BASE			0x0000
#define EEPROM_SIZE			0x0100
#define BBP_BASE			0x0000
#define BBP_SIZE			0x0020
#define RF_BASE				0x0004
#define RF_SIZE				0x000c

/*
 * Number of TX queues.
 */
#define NUM_TX_QUEUES			2

/*
 * Control/Status Registers(CSR).
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * CSR0: ASIC revision number.
 */
#define CSR0				0x0000

/*
 * CSR1: System control register.
 * SOFT_RESET: Software reset, 1: reset, 0: normal.
 * BBP_RESET: Hardware reset, 1: reset, 0, release.
 * HOST_READY: Host ready after initialization.
 */
#define CSR1				0x0004
#define CSR1_SOFT_RESET			FIELD32(0x00000001)
#define CSR1_BBP_RESET			FIELD32(0x00000002)
#define CSR1_HOST_READY			FIELD32(0x00000004)

/*
 * CSR2: System admin status register (invalid).
 */
#define CSR2				0x0008

/*
 * CSR3: STA MAC address register 0.
 */
#define CSR3				0x000c
#define CSR3_BYTE0			FIELD32(0x000000ff)
#define CSR3_BYTE1			FIELD32(0x0000ff00)
#define CSR3_BYTE2			FIELD32(0x00ff0000)
#define CSR3_BYTE3			FIELD32(0xff000000)

/*
 * CSR4: STA MAC address register 1.
 */
#define CSR4				0x0010
#define CSR4_BYTE4			FIELD32(0x000000ff)
#define CSR4_BYTE5			FIELD32(0x0000ff00)

/*
 * CSR5: BSSID register 0.
 */
#define CSR5				0x0014
#define CSR5_BYTE0			FIELD32(0x000000ff)
#define CSR5_BYTE1			FIELD32(0x0000ff00)
#define CSR5_BYTE2			FIELD32(0x00ff0000)
#define CSR5_BYTE3			FIELD32(0xff000000)

/*
 * CSR6: BSSID register 1.
 */
#define CSR6				0x0018
#define CSR6_BYTE4			FIELD32(0x000000ff)
#define CSR6_BYTE5			FIELD32(0x0000ff00)

/*
 * CSR7: Interrupt source register.
 * Write 1 to clear interrupt.
 * TBCN_EXPIRE: Beacon timer expired interrupt.
 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
 * TXDONE_TXRING: Tx ring transmit done interrupt.
 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
 * TXDONE_PRIORING: Priority ring transmit done interrupt.
 * RXDONE: Receive done interrupt.
 */
#define CSR7				0x001c
#define CSR7_TBCN_EXPIRE		FIELD32(0x00000001)
#define CSR7_TWAKE_EXPIRE		FIELD32(0x00000002)
#define CSR7_TATIMW_EXPIRE		FIELD32(0x00000004)
#define CSR7_TXDONE_TXRING		FIELD32(0x00000008)
#define CSR7_TXDONE_ATIMRING		FIELD32(0x00000010)
#define CSR7_TXDONE_PRIORING		FIELD32(0x00000020)
#define CSR7_RXDONE			FIELD32(0x00000040)

/*
 * CSR8: Interrupt mask register.
 * Write 1 to mask interrupt.
 * TBCN_EXPIRE: Beacon timer expired interrupt.
 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
 * TXDONE_TXRING: Tx ring transmit done interrupt.
 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
 * TXDONE_PRIORING: Priority ring transmit done interrupt.
 * RXDONE: Receive done interrupt.
 */
#define CSR8				0x0020
#define CSR8_TBCN_EXPIRE		FIELD32(0x00000001)
#define CSR8_TWAKE_EXPIRE		FIELD32(0x00000002)
#define CSR8_TATIMW_EXPIRE		FIELD32(0x00000004)
#define CSR8_TXDONE_TXRING		FIELD32(0x00000008)
#define CSR8_TXDONE_ATIMRING		FIELD32(0x00000010)
#define CSR8_TXDONE_PRIORING		FIELD32(0x00000020)
#define CSR8_RXDONE			FIELD32(0x00000040)

/*
 * CSR9: Maximum frame length register.
 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
 */
#define CSR9				0x0024
#define CSR9_MAX_FRAME_UNIT		FIELD32(0x00000f80)

/*
 * CSR11: Back-off control register.
 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
 * SLOT_TIME: Slot time, default is 20us for 802.11b.
 * LONG_RETRY: Long retry count.
 * SHORT_RETRY: Short retry count.
 */
#define CSR11				0x002c
#define CSR11_CWMIN			FIELD32(0x0000000f)
#define CSR11_CWMAX			FIELD32(0x000000f0)
#define CSR11_SLOT_TIME			FIELD32(0x00001f00)
#define CSR11_LONG_RETRY		FIELD32(0x00ff0000)
#define CSR11_SHORT_RETRY		FIELD32(0xff000000)

/*
 * CSR12: Synchronization configuration register 0.
 * All units in 1/16 TU.
 * BEACON_INTERVAL: Beacon interval, default is 100 TU.
 * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
 */
#define CSR12				0x0030
#define CSR12_BEACON_INTERVAL		FIELD32(0x0000ffff)
#define CSR12_CFP_MAX_DURATION		FIELD32(0xffff0000)

/*
 * CSR13: Synchronization configuration register 1.
 * All units in 1/16 TU.
 * ATIMW_DURATION: Atim window duration.
 * CFP_PERIOD: Cfp period, default is 0 TU.
 */
#define CSR13				0x0034
#define CSR13_ATIMW_DURATION		FIELD32(0x0000ffff)
#define CSR13_CFP_PERIOD		FIELD32(0x00ff0000)

/*
 * CSR14: Synchronization control register.
 * TSF_COUNT: Enable tsf auto counting.
 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 * TBCN: Enable tbcn with reload value.
 * TCFP: Enable tcfp & cfp / cp switching.
 * TATIMW: Enable tatimw & atim window switching.
 * BEACON_GEN: Enable beacon generator.
 * CFP_COUNT_PRELOAD: Cfp count preload value.
 * TBCM_PRELOAD: Tbcn preload value in units of 64us.
 */
#define CSR14				0x0038
#define CSR14_TSF_COUNT			FIELD32(0x00000001)
#define CSR14_TSF_SYNC			FIELD32(0x00000006)
#define CSR14_TBCN			FIELD32(0x00000008)
#define CSR14_TCFP			FIELD32(0x00000010)
#define CSR14_TATIMW			FIELD32(0x00000020)
#define CSR14_BEACON_GEN		FIELD32(0x00000040)
#define CSR14_CFP_COUNT_PRELOAD		FIELD32(0x0000ff00)
#define CSR14_TBCM_PRELOAD		FIELD32(0xffff0000)

/*
 * CSR15: Synchronization status register.
 * CFP: ASIC is in contention-free period.
 * ATIMW: ASIC is in ATIM window.
 * BEACON_SENT: Beacon is send.
 */
#define CSR15				0x003c
#define CSR15_CFP			FIELD32(0x00000001)
#define CSR15_ATIMW			FIELD32(0x00000002)
#define CSR15_BEACON_SENT		FIELD32(0x00000004)

/*
 * CSR16: TSF timer register 0.
 */
#define CSR16				0x0040
#define CSR16_LOW_TSFTIMER		FIELD32(0xffffffff)

/*
 * CSR17: TSF timer register 1.
 */
#define CSR17				0x0044
#define CSR17_HIGH_TSFTIMER		FIELD32(0xffffffff)

/*
 * CSR18: IFS timer register 0.
 * SIFS: Sifs, default is 10 us.
 * PIFS: Pifs, default is 30 us.
 */
#define CSR18				0x0048
#define CSR18_SIFS			FIELD32(0x0000ffff)
#define CSR18_PIFS			FIELD32(0xffff0000)

/*
 * CSR19: IFS timer register 1.
 * DIFS: Difs, default is 50 us.
 * EIFS: Eifs, default is 364 us.
 */
#define CSR19				0x004c
#define CSR19_DIFS			FIELD32(0x0000ffff)
#define CSR19_EIFS			FIELD32(0xffff0000)

/*
 * CSR20: Wakeup timer register.
 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 * AUTOWAKE: Enable auto wakeup / sleep mechanism.
 */
#define CSR20				0x0050
#define CSR20_DELAY_AFTER_TBCN		FIELD32(0x0000ffff)
#define CSR20_TBCN_BEFORE_WAKEUP	FIELD32(0x00ff0000)
#define CSR20_AUTOWAKE			FIELD32(0x01000000)

/*
 * CSR21: EEPROM control register.
 * RELOAD: Write 1 to reload eeprom content.
 * TYPE_93C46: 1: 93c46, 0:93c66.
 */
#define CSR21				0x0054
#define CSR21_RELOAD			FIELD32(0x00000001)
#define CSR21_EEPROM_DATA_CLOCK		FIELD32(0x00000002)
#define CSR21_EEPROM_CHIP_SELECT	FIELD32(0x00000004)
#define CSR21_EEPROM_DATA_IN		FIELD32(0x00000008)
#define CSR21_EEPROM_DATA_OUT		FIELD32(0x00000010)
#define CSR21_TYPE_93C46		FIELD32(0x00000020)

/*
 * CSR22: CFP control register.
 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
 */
#define CSR22				0x0058
#define CSR22_CFP_DURATION_REMAIN	FIELD32(0x0000ffff)
#define CSR22_RELOAD_CFP_DURATION	FIELD32(0x00010000)

/*
 * Transmit related CSRs.
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * TXCSR0: TX Control Register.
 * KICK_TX: Kick tx ring.
 * KICK_ATIM: Kick atim ring.
 * KICK_PRIO: Kick priority ring.
 * ABORT: Abort all transmit related ring operation.
 */
#define TXCSR0				0x0060
#define TXCSR0_KICK_TX			FIELD32(0x00000001)
#define TXCSR0_KICK_ATIM		FIELD32(0x00000002)
#define TXCSR0_KICK_PRIO		FIELD32(0x00000004)
#define TXCSR0_ABORT			FIELD32(0x00000008)

/*
 * TXCSR1: TX Configuration Register.
 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
 * TSF_OFFSET: Insert tsf offset.
 * AUTORESPONDER: Enable auto responder which include ack & cts.
 */
#define TXCSR1				0x0064
#define TXCSR1_ACK_TIMEOUT		FIELD32(0x000001ff)
#define TXCSR1_ACK_CONSUME_TIME		FIELD32(0x0003fe00)
#define TXCSR1_TSF_OFFSET		FIELD32(0x00fc0000)
#define TXCSR1_AUTORESPONDER		FIELD32(0x01000000)

/*
 * TXCSR2: Tx descriptor configuration register.
 * TXD_SIZE: Tx descriptor size, default is 48.
 * NUM_TXD: Number of tx entries in ring.
 * NUM_ATIM: Number of atim entries in ring.
 * NUM_PRIO: Number of priority entries in ring.
 */
#define TXCSR2				0x0068
#define TXCSR2_TXD_SIZE			FIELD32(0x000000ff)
#define TXCSR2_NUM_TXD			FIELD32(0x0000ff00)
#define TXCSR2_NUM_ATIM			FIELD32(0x00ff0000)
#define TXCSR2_NUM_PRIO			FIELD32(0xff000000)

/*
 * TXCSR3: TX Ring Base address register.
 */
#define TXCSR3				0x006c
#define TXCSR3_TX_RING_REGISTER		FIELD32(0xffffffff)

/*
 * TXCSR4: TX Atim Ring Base address register.
 */
#define TXCSR4				0x0070
#define TXCSR4_ATIM_RING_REGISTER	FIELD32(0xffffffff)

/*
 * TXCSR5: TX Prio Ring Base address register.
 */
#define TXCSR5				0x0074
#define TXCSR5_PRIO_RING_REGISTER	FIELD32(0xffffffff)

/*
 * TXCSR6: Beacon Base address register.
 */
#define TXCSR6				0x0078
#define TXCSR6_BEACON_RING_REGISTER	FIELD32(0xffffffff)

/*
 * TXCSR7: Auto responder control register.
 * AR_POWERMANAGEMENT: Auto responder power management bit.
 */
#define TXCSR7				0x007c
#define TXCSR7_AR_POWERMANAGEMENT	FIELD32(0x00000001)

/*
 * Receive related CSRs.
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * RXCSR0: RX Control Register.
 * DISABLE_RX: Disable rx engine.
 * DROP_CRC: Drop crc error.
 * DROP_PHYSICAL: Drop physical error.
 * DROP_CONTROL: Drop control frame.
 * DROP_NOT_TO_ME: Drop not to me unicast frame.
 * DROP_TODS: Drop frame tods bit is true.
 * DROP_VERSION_ERROR: Drop version error frame.
 * PASS_CRC: Pass all packets with crc attached.
 */
#define RXCSR0				0x0080
#define RXCSR0_DISABLE_RX		FIELD32(0x00000001)
#define RXCSR0_DROP_CRC			FIELD32(0x00000002)
#define RXCSR0_DROP_PHYSICAL		FIELD32(0x00000004)
#define RXCSR0_DROP_CONTROL		FIELD32(0x00000008)
#define RXCSR0_DROP_NOT_TO_ME		FIELD32(0x00000010)
#define RXCSR0_DROP_TODS		FIELD32(0x00000020)
#define RXCSR0_DROP_VERSION_ERROR	FIELD32(0x00000040)
#define RXCSR0_PASS_CRC			FIELD32(0x00000080)

/*
 * RXCSR1: RX descriptor configuration register.
 * RXD_SIZE: Rx descriptor size, default is 32b.
 * NUM_RXD: Number of rx entries in ring.
 */
#define RXCSR1				0x0084
#define RXCSR1_RXD_SIZE			FIELD32(0x000000ff)
#define RXCSR1_NUM_RXD			FIELD32(0x0000ff00)

/*
 * RXCSR2: RX Ring base address register.
 */
#define RXCSR2				0x0088
#define RXCSR2_RX_RING_REGISTER		FIELD32(0xffffffff)

/*
 * RXCSR3: BBP ID register for Rx operation.
 * BBP_ID#: BBP register # id.
 * BBP_ID#_VALID: BBP register # id is valid or not.
 */
#define RXCSR3				0x0090
#define RXCSR3_BBP_ID0			FIELD32(0x0000007f)
#define RXCSR3_BBP_ID0_VALID		FIELD32(0x00000080)
#define RXCSR3_BBP_ID1			FIELD32(0x00007f00)
#define RXCSR3_BBP_ID1_VALID		FIELD32(0x00008000)
#define RXCSR3_BBP_ID2			FIELD32(0x007f0000)
#define RXCSR3_BBP_ID2_VALID		FIELD32(0x00800000)
#define RXCSR3_BBP_ID3			FIELD32(0x7f000000)
#define RXCSR3_BBP_ID3_VALID		FIELD32(0x80000000)

/*
 * RXCSR4: BBP ID register for Rx operation.
 * BBP_ID#: BBP register # id.
 * BBP_ID#_VALID: BBP register # id is valid or not.
 */
#define RXCSR4				0x0094
#define RXCSR4_BBP_ID4			FIELD32(0x0000007f)
#define RXCSR4_BBP_ID4_VALID		FIELD32(0x00000080)
#define RXCSR4_BBP_ID5			FIELD32(0x00007f00)
#define RXCSR4_BBP_ID5_VALID		FIELD32(0x00008000)

/*
 * ARCSR0: Auto Responder PLCP config register 0.
 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
 */
#define ARCSR0				0x0098
#define ARCSR0_AR_BBP_DATA0		FIELD32(0x000000ff)
#define ARCSR0_AR_BBP_ID0		FIELD32(0x0000ff00)
#define ARCSR0_AR_BBP_DATA1		FIELD32(0x00ff0000)
#define ARCSR0_AR_BBP_ID1		FIELD32(0xff000000)

/*
 * ARCSR1: Auto Responder PLCP config register 1.
 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
 */
#define ARCSR1				0x009c
#define ARCSR1_AR_BBP_DATA2		FIELD32(0x000000ff)
#define ARCSR1_AR_BBP_ID2		FIELD32(0x0000ff00)
#define ARCSR1_AR_BBP_DATA3		FIELD32(0x00ff0000)
#define ARCSR1_AR_BBP_ID3		FIELD32(0xff000000)

/*
 * Miscellaneous Registers.
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * PCICSR: PCI control register.
 * BIG_ENDIAN: 1: big endian, 0: little endian.
 * RX_TRESHOLD: Rx threshold in dw to start pci access
 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
 * TX_TRESHOLD: Tx threshold in dw to start pci access
 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
 */
#define PCICSR				0x008c