path: root/drivers/net/wireless/mwifiex/main.h

/*
 * Marvell Wireless LAN device driver: major data structures and prototypes
 *
 * Copyright (C) 2011, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef _MWIFIEX_MAIN_H_
#define _MWIFIEX_MAIN_H_

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/semaphore.h>
#include <linux/ip.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/etherdevice.h>
#include <net/sock.h>
#include <net/lib80211.h>
#include <linux/firmware.h>
#include <linux/ctype.h>

#include "decl.h"
#include "ioctl.h"
#include "util.h"
#include "fw.h"
#include "pcie.h"

extern const char driver_version[];

enum {
	MWIFIEX_ASYNC_CMD,
	MWIFIEX_SYNC_CMD
};

#define MWIFIEX_MAX_AP				64

#define MWIFIEX_DEFAULT_WATCHDOG_TIMEOUT	(5 * HZ)

#define MWIFIEX_TIMER_10S			10000
#define MWIFIEX_TIMER_1S			1000

#define MAX_TX_PENDING      100
#define LOW_TX_PENDING      80

#define MWIFIEX_UPLD_SIZE               (2312)

#define MAX_EVENT_SIZE                  1024

#define ARP_FILTER_MAX_BUF_SIZE         68

#define MWIFIEX_KEY_BUFFER_SIZE			16
#define MWIFIEX_DEFAULT_LISTEN_INTERVAL 10
#define MWIFIEX_MAX_REGION_CODE         7

#define DEFAULT_BCN_AVG_FACTOR          8
#define DEFAULT_DATA_AVG_FACTOR         8

#define FIRST_VALID_CHANNEL				0xff
#define DEFAULT_AD_HOC_CHANNEL			6
#define DEFAULT_AD_HOC_CHANNEL_A		36

#define DEFAULT_BCN_MISS_TIMEOUT		5

#define MAX_SCAN_BEACON_BUFFER			8000

#define SCAN_BEACON_ENTRY_PAD			6

#define MWIFIEX_PASSIVE_SCAN_CHAN_TIME	110
#define MWIFIEX_ACTIVE_SCAN_CHAN_TIME	30
#define MWIFIEX_SPECIFIC_SCAN_CHAN_TIME	30

#define SCAN_RSSI(RSSI)					(0x100 - ((u8)(RSSI)))

#define MWIFIEX_MAX_TOTAL_SCAN_TIME	(MWIFIEX_TIMER_10S - MWIFIEX_TIMER_1S)

#define MWIFIEX_MAX_SCAN_DELAY_CNT			50
#define MWIFIEX_MAX_EMPTY_TX_Q_CNT			10
#define MWIFIEX_SCAN_DELAY_MSEC				20

#define MWIFIEX_MIN_TX_PENDING_TO_CANCEL_SCAN		2

#define RSN_GTK_OUI_OFFSET				2

#define MWIFIEX_OUI_NOT_PRESENT			0
#define MWIFIEX_OUI_PRESENT				1

#define PKT_TYPE_MGMT	0xE5

/*
 * Do not check for data_received for USB, as data_received
 * is handled in mwifiex_usb_recv for USB
 */
#define IS_CARD_RX_RCVD(adapter) (adapter->cmd_resp_received || \
				adapter->event_received || \
				((adapter->iface_type != MWIFIEX_USB) && \
				adapter->data_received) || \
				((adapter->iface_type == MWIFIEX_USB) && \
				!skb_queue_empty(&adapter->usb_rx_data_q)))

#define MWIFIEX_TYPE_CMD				1
#define MWIFIEX_TYPE_DATA				0
#define MWIFIEX_TYPE_EVENT				3

#define MAX_BITMAP_RATES_SIZE			10

#define MAX_CHANNEL_BAND_BG     14
#define MAX_CHANNEL_BAND_A      165

#define MAX_FREQUENCY_BAND_BG   2484

#define MWIFIEX_EVENT_HEADER_LEN           4
#define MWIFIEX_UAP_EVENT_EXTRA_HEADER	   2

#define MWIFIEX_TYPE_LEN			4
#define MWIFIEX_USB_TYPE_CMD			0xF00DFACE
#define MWIFIEX_USB_TYPE_DATA			0xBEADC0DE
#define MWIFIEX_USB_TYPE_EVENT			0xBEEFFACE

/* Threshold for tx_timeout_cnt before we trigger a card reset */
#define TX_TIMEOUT_THRESHOLD	6

struct mwifiex_dbg {
	u32 num_cmd_host_to_card_failure;
	u32 num_cmd_sleep_cfm_host_to_card_failure;
	u32 num_tx_host_to_card_failure;
	u32 num_event_deauth;
	u32 num_event_disassoc;
	u32 num_event_link_lost;
	u32 num_cmd_deauth;
	u32 num_cmd_assoc_success;
	u32 num_cmd_assoc_failure;
	u32 num_tx_timeout;
	u32 num_cmd_timeout;
	u16 timeout_cmd_id;
	u16 timeout_cmd_act;
	u16 last_cmd_id[DBG_CMD_NUM];
	u16 last_cmd_act[DBG_CMD_NUM];
	u16 last_cmd_index;
	u16 last_cmd_resp_id[DBG_CMD_NUM];
	u16 last_cmd_resp_index;
	u16 last_event[DBG_CMD_NUM];
	u16 last_event_index;
};

enum MWIFIEX_HARDWARE_STATUS {
	MWIFIEX_HW_STATUS_READY,
	MWIFIEX_HW_STATUS_INITIALIZING,
	MWIFIEX_HW_STATUS_FW_READY,
	MWIFIEX_HW_STATUS_INIT_DONE,
	MWIFIEX_HW_STATUS_RESET,
	MWIFIEX_HW_STATUS_CLOSING,
	MWIFIEX_HW_STATUS_NOT_READY
};

enum MWIFIEX_802_11_POWER_MODE {
	MWIFIEX_802_11_POWER_MODE_CAM,
	MWIFIEX_802_11_POWER_MODE_PSP
};

struct mwifiex_tx_param {
	u32 next_pkt_len;
};

enum MWIFIEX_PS_STATE {
	PS_STATE_AWAKE,
	PS_STATE_PRE_SLEEP,
	PS_STATE_SLEEP_CFM,
	PS_STATE_SLEEP
};

enum mwifiex_iface_type {
	MWIFIEX_SDIO,
	MWIFIEX_PCIE,
	MWIFIEX_USB
};

struct mwifiex_add_ba_param {
	u32 tx_win_size;
	u32 rx_win_size;
	u32 timeout;
};

struct mwifiex_tx_aggr {
	u8 ampdu_user;
	u8 ampdu_ap;
	u8 amsdu;
};

struct mwifiex_ra_list_tbl {
	struct list_head list;
	struct sk_buff_head skb_head;
	u8 ra[ETH_ALEN];
	u32 is_11n_enabled;
	u16 max_amsdu;
	u16 ba_pkt_count;
	u8 ba_packet_thr;
	u16 total_pkt_count;
};

struct mwifiex_tid_tbl {
	struct list_head ra_list;
};

#define WMM_HIGHEST_PRIORITY		7
#define HIGH_PRIO_TID				7
#define LOW_PRIO_TID				0

struct mwifiex_wmm_desc {
	struct mwifiex_tid_tbl tid_tbl_ptr[MAX_NUM_TID];
	u32 packets_out[MAX_NUM_TID];
	/* spin lock to protect ra_list */
	spinlock_t ra