path: root/drivers/net/wireless/ath9k/ath9k.h

/*
 * Copyright (c) 2008 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef ATH9K_H
#define ATH9K_H

#include <linux/io.h>

#define ATHEROS_VENDOR_ID	0x168c

#define AR5416_DEVID_PCI	0x0023
#define AR5416_DEVID_PCIE	0x0024
#define AR9160_DEVID_PCI	0x0027
#define AR9280_DEVID_PCI	0x0029
#define AR9280_DEVID_PCIE	0x002a

#define AR5416_AR9100_DEVID	0x000b

#define	AR_SUBVENDOR_ID_NOG	0x0e11
#define AR_SUBVENDOR_ID_NEW_A	0x7065

#define ATH9K_TXERR_XRETRY         0x01
#define ATH9K_TXERR_FILT           0x02
#define ATH9K_TXERR_FIFO           0x04
#define ATH9K_TXERR_XTXOP          0x08
#define ATH9K_TXERR_TIMER_EXPIRED  0x10

#define ATH9K_TX_BA                0x01
#define ATH9K_TX_PWRMGMT           0x02
#define ATH9K_TX_DESC_CFG_ERR      0x04
#define ATH9K_TX_DATA_UNDERRUN     0x08
#define ATH9K_TX_DELIM_UNDERRUN    0x10
#define ATH9K_TX_SW_ABORTED        0x40
#define ATH9K_TX_SW_FILTERED       0x80

#define NBBY    8

struct ath_tx_status {
	u32 ts_tstamp;
	u16 ts_seqnum;
	u8 ts_status;
	u8 ts_ratecode;
	u8 ts_rateindex;
	int8_t ts_rssi;
	u8 ts_shortretry;
	u8 ts_longretry;
	u8 ts_virtcol;
	u8 ts_antenna;
	u8 ts_flags;
	int8_t ts_rssi_ctl0;
	int8_t ts_rssi_ctl1;
	int8_t ts_rssi_ctl2;
	int8_t ts_rssi_ext0;
	int8_t ts_rssi_ext1;
	int8_t ts_rssi_ext2;
	u8 pad[3];
	u32 ba_low;
	u32 ba_high;
	u32 evm0;
	u32 evm1;
	u32 evm2;
};

struct ath_rx_status {
	u32 rs_tstamp;
	u16 rs_datalen;
	u8 rs_status;
	u8 rs_phyerr;
	int8_t rs_rssi;
	u8 rs_keyix;
	u8 rs_rate;
	u8 rs_antenna;
	u8 rs_more;
	int8_t rs_rssi_ctl0;
	int8_t rs_rssi_ctl1;
	int8_t rs_rssi_ctl2;
	int8_t rs_rssi_ext0;
	int8_t rs_rssi_ext1;
	int8_t rs_rssi_ext2;
	u8 rs_isaggr;
	u8 rs_moreaggr;
	u8 rs_num_delims;
	u8 rs_flags;
	u32 evm0;
	u32 evm1;
	u32 evm2;
};

#define ATH9K_RXERR_CRC           0x01
#define ATH9K_RXERR_PHY           0x02
#define ATH9K_RXERR_FIFO          0x04
#define ATH9K_RXERR_DECRYPT       0x08
#define ATH9K_RXERR_MIC           0x10

#define ATH9K_RX_MORE             0x01
#define ATH9K_RX_MORE_AGGR        0x02
#define ATH9K_RX_GI               0x04
#define ATH9K_RX_2040             0x08
#define ATH9K_RX_DELIM_CRC_PRE    0x10
#define ATH9K_RX_DELIM_CRC_POST   0x20
#define ATH9K_RX_DECRYPT_BUSY     0x40

#define ATH9K_RXKEYIX_INVALID	((u8)-1)
#define ATH9K_TXKEYIX_INVALID	((u32)-1)

struct ath_desc {
	u32 ds_link;
	u32 ds_data;
	u32 ds_ctl0;
	u32 ds_ctl1;
	u32 ds_hw[20];
	union {
		struct ath_tx_status tx;
		struct ath_rx_status rx;
		void *stats;
	} ds_us;
	void *ds_vdata;
} __packed;

#define	ds_txstat	ds_us.tx
#define	ds_rxstat	ds_us.rx
#define ds_stat		ds_us.stats

#define ATH9K_TXDESC_CLRDMASK		0x0001
#define ATH9K_TXDESC_NOACK		0x0002
#define ATH9K_TXDESC_RTSENA		0x0004
#define ATH9K_TXDESC_CTSENA		0x0008
#define ATH9K_TXDESC_INTREQ		0x0010
#define ATH9K_TXDESC_VEOL		0x0020
#define ATH9K_TXDESC_EXT_ONLY		0x0040
#define ATH9K_TXDESC_EXT_AND_CTL	0x0080
#define ATH9K_TXDESC_VMF		0x0100
#define ATH9K_TXDESC_FRAG_IS_ON 	0x0200

#define ATH9K_RXDESC_INTREQ		0x0020

enum wireless_mode {
	ATH9K_MODE_11A = 0,
	ATH9K_MODE_11B = 2,
	ATH9K_MODE_11G = 3,
	ATH9K_MODE_11NA_HT20 = 6,
	ATH9K_MODE_11NG_HT20 = 7,
	ATH9K_MODE_11NA_HT40PLUS = 8,
	ATH9K_MODE_11NA_HT40MINUS = 9,
	ATH9K_MODE_11NG_HT40PLUS = 10,
	ATH9K_MODE_11NG_HT40MINUS = 11,
	ATH9K_MODE_MAX
};

enum ath9k_hw_caps {
	ATH9K_HW_CAP_CHAN_SPREAD		= BIT(0),
	ATH9K_HW_CAP_MIC_AESCCM                 = BIT(1),
	ATH9K_HW_CAP_MIC_CKIP                   = BIT(2),
	ATH9K_HW_CAP_MIC_TKIP                   = BIT(3),
	ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(4),
	ATH9K_HW_CAP_CIPHER_CKIP                = BIT(5),
	ATH9K_HW_CAP_CIPHER_TKIP                = BIT(6),
	ATH9K_HW_CAP_VEOL                       = BIT(7),
	ATH9K_HW_CAP_BSSIDMASK                  = BIT(8),
	ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(9),
	ATH9K_HW_CAP_CHAN_HALFRATE              = BIT(10),
	ATH9K_HW_CAP_CHAN_QUARTERRATE           = BIT(11),
	ATH9K_HW_CAP_HT                         = BIT(12),
	ATH9K_HW_CAP_GTT                        = BIT(13),
	ATH9K_HW_CAP_FASTCC                     = BIT(14),
	ATH9K_HW_CAP_RFSILENT                   = BIT(15),
	ATH9K_HW_CAP_WOW                        = BIT(16),
	ATH9K_HW_CAP_CST                        = BIT(17),
	ATH9K_HW_CAP_ENHANCEDPM                 = BIT(18),
	ATH9K_HW_CAP_AUTOSLEEP                  = BIT(19),
	ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(20),
	ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT     = BIT(21),
};

enum ath9k_capability_type {
	ATH9K_CAP_CIPHER = 0,
	ATH9K_CAP_TKIP_MIC,
	ATH9K_CAP_TKIP_SPLIT,
	ATH9K_CAP_PHYCOUNTERS,
	ATH9K_CAP_DIVERSITY,
	ATH9K_CAP_TXPOW,
	ATH9K_CAP_PHYDIAG,
	ATH9K_CAP_MCAST_KEYSRCH,
	ATH9K_CAP_TSF_ADJUST,
	ATH9K_CAP_WME_TKIPMIC,
	ATH9K_CAP_RFSILENT,
	ATH9K_CAP_ANT_CFG_2GHZ,
	ATH9K_CAP_ANT_CFG_5GHZ
};

struct ath9k_hw_capabilities {
	u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw