path: root/drivers/net/sungem.h

/* $Id: sungem.h,v 1.10.2.4 2002/03/11 08:54:48 davem Exp $
 * sungem.h: Definitions for Sun GEM ethernet driver.
 *
 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
 */

#ifndef _SUNGEM_H
#define _SUNGEM_H

/* Global Registers */
#define GREG_SEBSTATE	0x0000UL	/* SEB State Register		*/
#define GREG_CFG	0x0004UL	/* Configuration Register	*/
#define GREG_STAT	0x000CUL	/* Status Register		*/
#define GREG_IMASK	0x0010UL	/* Interrupt Mask Register	*/
#define GREG_IACK	0x0014UL	/* Interrupt ACK Register	*/
#define GREG_STAT2	0x001CUL	/* Alias of GREG_STAT		*/
#define GREG_PCIESTAT	0x1000UL	/* PCI Error Status Register	*/
#define GREG_PCIEMASK	0x1004UL	/* PCI Error Mask Register	*/
#define GREG_BIFCFG	0x1008UL	/* BIF Configuration Register	*/
#define GREG_BIFDIAG	0x100CUL	/* BIF Diagnostics Register	*/
#define GREG_SWRST	0x1010UL	/* Software Reset Register	*/

/* Global SEB State Register */
#define GREG_SEBSTATE_ARB	0x00000003	/* State of Arbiter		*/
#define GREG_SEBSTATE_RXWON	0x00000004	/* RX won internal arbitration	*/

/* Global Configuration Register */
#define GREG_CFG_IBURST		0x00000001	/* Infinite Burst		*/
#define GREG_CFG_TXDMALIM	0x0000003e	/* TX DMA grant limit		*/
#define GREG_CFG_RXDMALIM	0x000007c0	/* RX DMA grant limit		*/
#define GREG_CFG_RONPAULBIT	0x00000800	/* Use mem read multiple for PCI read
						 * after infinite burst (Apple) */
#define GREG_CFG_ENBUG2FIX	0x00001000	/* Fix Rx hang after overflow */

/* Global Interrupt Status Register.
 *
 * Reading this register automatically clears bits 0 through 6.
 * This auto-clearing does not occur when the alias at GREG_STAT2
 * is read instead.  The rest of the interrupt bits only clear when
 * the secondary interrupt status register corresponding to that
 * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by
 * reading PCS_ISTAT).
 */
#define GREG_STAT_TXINTME	0x00000001	/* TX INTME frame transferred	*/
#define GREG_STAT_TXALL		0x00000002	/* All TX frames transferred	*/
#define GREG_STAT_TXDONE	0x00000004	/* One TX frame transferred	*/
#define GREG_STAT_RXDONE	0x00000010	/* One RX frame arrived		*/
#define GREG_STAT_RXNOBUF	0x00000020	/* No free RX buffers available	*/
#define GREG_STAT_RXTAGERR	0x00000040	/* RX tag framing is corrupt	*/
#define GREG_STAT_PCS		0x00002000	/* PCS signalled interrupt	*/
#define GREG_STAT_TXMAC		0x00004000	/* TX MAC signalled interrupt	*/
#define GREG_STAT_RXMAC		0x00008000	/* RX MAC signalled interrupt	*/
#define GREG_STAT_MAC		0x00010000	/* MAC Control signalled irq	*/
#define GREG_STAT_MIF		0x00020000	/* MIF signalled interrupt	*/
#define GREG_STAT_PCIERR	0x00040000	/* PCI Error interrupt		*/
#define GREG_STAT_TXNR		0xfff80000	/* == TXDMA_TXDONE reg val	*/
#define GREG_STAT_TXNR_SHIFT	19

#define GREG_STAT_ABNORMAL	(GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \
				 GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \
				 GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR)

#define GREG_STAT_NAPI		(GREG_STAT_TXALL  | GREG_STAT_TXINTME | \
				 GREG_STAT_RXDONE | GREG_STAT_ABNORMAL)

/* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT.
 * Bits set in GREG_IMASK will prevent that interrupt type from being
 * signalled to the cpu.  GREG_IACK can be used to clear specific top-level
 * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6.
 * Setting the bit will clear that interrupt, clear bits will have no effect
 * on GREG_STAT.
 */

/* Global PCI Error Status Register */
#define GREG_PCIESTAT_BADACK	0x00000001	/* No ACK64# during ABS64 cycle	*/
#define GREG_PCIESTAT_DTRTO	0x00000002	/* Delayed transaction timeout	*/
#define GREG_PCIESTAT_OTHER	0x00000004	/* Other PCI error, check cfg space */

/* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT.
 * Bits set in GREG_PCIEMASK will prevent that interrupt type from being
 * signalled to the cpu.
 */

/* Global BIF Configuration Register */
#define GREG_BIFCFG_SLOWCLK	0x00000001	/* Set if PCI runs < 25Mhz	*/
#define GREG_BIFCFG_B64DIS	0x00000002	/* Disable 64bit wide data cycle*/
#define GREG_BIFCFG_M66EN	0x00000004	/* Set if on 66Mhz PCI segment	*/

/* Global BIF Diagnostics Register */
#define GREG_BIFDIAG_BURSTSM	0x007f0000	/* PCI Burst state machine	*/
#define GREG_BIFDIAG_BIFSM	0xff000000	/* BIF state machine		*/

/* Global Software Reset Register.
 *
 * This register is used to perform a global reset of the RX and TX portions
 * of the GEM asic.  Setting the RX or TX reset bit will start the reset.
 * The driver _MUST_ poll these bits until they clear.  One may not attempt
 * to program any other part of GEM until the bits clear.
 */
#define GREG_SWRST_TXRST	0x00000001	/* TX Software Reset		*/
#define GREG_SWRST_RXRST	0x00000002	/* RX Software Reset		*/
#define GREG_SWRST_RSTOUT	0x00000004	/* Force RST# pin active	*/
#define GREG_SWRST_CACHESIZE	0x00ff0000	/* RIO only: cache line size	*/
#define GREG_SWRST_CACHE_SHIFT	16

/* TX DMA Registers */
#define TXDMA_KICK	0x2000UL	/* TX Kick Register		*/
#define TXDMA_CFG	0x2004UL	/* TX Configuration Register	*/
#define TXDMA_DBLOW	0x2008UL	/* TX Desc. Base Low		*/
#define TXDMA_DBHI	0x200CUL	/* TX Desc. Base High		*/
#define TXDMA_FWPTR	0x2014UL	/* TX FIFO Write Pointer	*/
#define TXDMA_FSWPTR	0x2018UL	/* TX FIFO Shadow Write Pointer	*/
#define TXDMA_FRPTR	0x201CUL	/* TX FIFO Read Pointer		*/
#define TXDMA_FSRPTR	0x2020UL	/* TX FIFO Shadow Read Pointer	*/
#define TXDMA_PCNT	0x2024UL	/* TX FIFO Packet Counter	*/
#define TXDMA_SMACHINE	0x2028UL	/* TX State Machine Register	*/
#define TXDMA_DPLOW	0x2030UL	/* TX Data Pointer Low		*/
#define TXDMA_DPHI	0x2034UL	/* TX Data Pointer High		*/
#define TXDMA_TXDONE	0x2100UL	/* TX Completion Register	*/
#define TXDMA_FADDR	0x2104UL	/* TX FIFO Address		*/
#define TXDMA_FTAG	0x2108UL	/* TX FIFO Tag			*/
#define TXDMA_DLOW	0x210CUL	/* TX FIFO Data Low		*/
#define TXDMA_DHIT1	0x2110UL	/* TX FIFO Data HighT1		*/
#define TXDMA_DHIT0	0x2114UL	/* TX FIFO Data HighT0		*/
#define TXDMA_FSZ	0x2118UL	/* TX FIFO Size			*/

/* TX Kick Register.
 *
 * This 13-bit register is programmed by the driver to hold the descriptor
 * entry index which follows the last valid transmit descriptor.
 */

/* TX Completion Register.
 *
 * This 13-bit register is updated by GEM to hold to descriptor entry index
 * which follows the last descriptor already processed by GEM.  Note that
 * this value is mirrored in GREG_STAT which eliminates the need to even
 * access this register in the driver during interrupt processing.
 */

/* TX Configuration Register.
 *
 * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature
 * that was meant to be used with jumbo packets.  It should be set to the
 * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors.
 */
#define TXDMA_CFG_ENABLE	0x00000001	/* Enable TX DMA channel	*/
#define TXDMA_CFG_RINGSZ	0x0000001e	/* TX descriptor ring size	*/
#define TXDMA_CFG_RINGSZ_32	0x00000000	/* 32 TX descriptors		*/
#define TXDMA_CFG_RINGSZ_64	0x00000002	/* 64 TX descriptors		*/
#define TXDMA_CFG_RINGSZ_128	0x00000004	/* 128 TX descriptors		*/
#define TXDMA_CFG_RINGSZ_256	0x00000006	/* 256 TX descriptors		*/
#define TXDMA_CFG_RINGSZ_512	0x00000008	/* 512 TX descriptors		*/
#define TXDMA_CFG_RINGSZ_1K	0x0000000a	/* 1024 TX descriptors		*/
#define TXDMA_CFG_RINGSZ_2K	0x0000000c	/* 2048 TX descriptors		*/
#define TXDMA_CFG_RINGSZ_4K	0x0000000e	/* 4096 TX descriptors		*/
#define TXDMA_CFG_RINGSZ_8K	0x00000010	/* 8192 TX descriptors		*/
#define TXDMA_CFG_PIOSEL	0x00000020	/* Enable TX FIFO PIO from cpu	*/
#define TXDMA_CFG_FTHRESH	0x001ffc00	/* TX FIFO Threshold, obsolete	*/
#define TXDMA_CFG_PMODE		0x00200000	/* TXALL irq means TX FIFO empty*/

/* TX Descriptor Base Low/High.
 *
 * These two registers store the 53 most significant bits of the base address
 * of the TX descriptor table.  The 11 least significant bits are always
 * zero.  As a result, the TX descriptor table must be 2K aligned.
 */

/* The rest of the TXDMA_* registers are for diagnostics and debug, I will document
 * them later. -DaveM
 */

/* WakeOnLan Registers	*/
#define WOL_MATCH0	0x3000UL
#define WOL_MATCH1	0x3004UL
#define WOL_MATCH2	0x3008UL
#define WOL_MCOUNT	0x300CUL
#define WOL_WAKECSR	0x3010UL

/* WOL Match count register
 */
#define WOL_MCOUNT_N		0x00000010
#define WOL_MCOUNT_M		0x00000000 /* 0 << 8 */

#define WOL_WAKECSR_ENABLE	0x00000001
#define WOL_WAKECSR_MII		0x00000002
#define WOL_WAKECSR_SEEN	0x00000004
#define WOL_WAKECSR_FILT_UCAST	0x00000008
#define WOL_WAKECSR_FILT_MCAST	0x00000010
#define WOL_WAKECSR_FILT_BCAST	0x00000020
#define WOL_WAKECSR_FILT_SEEN	0x00000040


/* Receive DMA Registers */
#define RXDMA_CFG	0x4000UL	/* RX Configuration Register	*/
#define RXDMA_DBLOW	0x4004UL	/* RX Descriptor Base Low	*/
#define RXDMA_DBHI	0x4008UL	/* RX Descriptor Base High	*/
#define RXDMA_FWPTR	0x400CUL	/* RX FIFO Write Pointer	*/
#define RXDMA_FSWPTR	0x4010UL	/* RX FIFO Shadow Write Pointer	*/
#define RXDMA_FRPTR	0x4014UL	/* RX FIFO Read Pointer		*/
#define RXDMA_PCNT	0x4018UL	/* RX FIFO Packet Counter	*/
#define RXDMA_SMACHINE	0x401CUL	/* RX State Machine Register	*/
#define RXDMA_PTHRESH	0x4020UL	/* Pause Thresholds		*/
#define RXDMA_DPLOW	0x4024UL	/* RX Data Pointer Low		*/
#define RXDMA_DPHI	0x4028UL	/* RX Data Pointer High		*/
#define RXDMA_KICK	0x4100UL	/* RX Kick Register		*/
#define RXDMA_DONE	0x4104UL	/* RX Completion Register	*/
#define RXDMA_BLANK	0x4108UL	/* RX Blanking Register		*/
#define RXDMA_FADDR	0x410CUL	/* RX FIFO Address		*/
#define RXDMA_FTAG	0x4110UL	/* RX FIFO Tag			*/
#define RXDMA_DLOW	0x4114UL	/* RX FIFO Data Low		*/
#define RXDMA_DHIT1	0x4118UL	/* RX FIFO Data HighT0		*/
#define RXDMA_DHIT0	0x411CUL	/* RX FIFO Data HighT1		*/
#define RXDMA_FSZ	0x4120UL	/* RX FIFO Size			*/

/* RX Configuration Register. */
#define RXDMA_CFG_ENABLE	0x00000001	/* Enable RX DMA channel	*/
#define RXDMA_CFG_RINGSZ	0x0000001e	/* RX descriptor ring size	*/
#define RXDMA_CFG_RINGSZ_32	0x00000000	/* - 32   entries		*/
#define RXDMA_CFG_RINGSZ_64	0x00000002	/* - 64   entries		*/
#define RXDMA_CFG_RINGSZ_128	0x00000004	/* - 128  entries		*/
#define RXDMA_CFG_RINGSZ_256	0x00000006	/* - 256  entries		*/
#define RXDMA_CFG_RINGSZ_512	0x00000008	/* - 512  entries		*/
#define RXDMA_CFG_RINGSZ_1K	0x0000000a	/* - 1024 entries		*/
#define RXDMA_CFG_RINGSZ_2K	0x0000000c	/* - 2048 entries		*/
#define RXDMA_CFG_RINGSZ_4K	0x0000000e	/* - 4096 entries		*/
#define RXDMA_CFG_RINGSZ_8K	0x00000010	/* - 8192 entries		*/
#define RXDMA_CFG_RINGSZ_BDISAB	0x00000020	/* Disable RX desc batching	*/
#define RXDMA_CFG_FBOFF		0x00001c00	/* Offset of first data byte	*/
#define RXDMA_CFG_CSUMOFF	0x000fe000	/* Skip bytes before csum calc	*/
#define RXDMA_CFG_FTHRESH	0x07000000	/* RX FIFO dma start threshold	*/
#define RXDMA_CFG_FTHRESH_64	0x00000000	/* - 64   bytes			*/
#define RXDMA_CFG_FTHRESH_128	0x01000000	/* - 128  bytes			*/
#define RXDMA_CFG_FTHRESH_256	0x02000000	/* - 256  bytes			*/
#define RXDMA_CFG_FTHRESH_512	0x03000000	/* - 512  bytes			*/
#define RXDMA_CFG_FTHRESH_1K	0x04000000	/* - 1024 bytes			*/
#define RXDMA_CFG_FTHRESH_2K	0x05000000	/* - 2048 bytes			*/

/* RX Descriptor Base Low/High.
 *
 * These two registers store the 53 most significant bits of the base address
 * of the RX descriptor table.  The 11 least significant bits are always
 * zero.  As a result, the RX descriptor table must be 2K aligned.
 */

/* RX PAUSE Thresholds.
 *
 * These values determine when XOFF and XON PAUSE frames are emitted by
 * GEM.  The thresholds measure RX FIFO occupancy in units of 64 bytes.
 */
#define RXDMA_PTHRESH_OFF	0x000001ff	/* XOFF emitted w/FIFO > this	*/
#define RXDMA_PTHRESH_ON	0x001ff000	/* XON emitted w/FIFO < this	*/

/* RX Kick Register.
 *
 * This 13-bit register is written by the host CPU and holds the last
 * valid RX descriptor number plus one.  This is, if 'N' is written to
 * this register, it means that all RX descriptors up to but excluding
 * 'N' are valid.
 *
 * The hardware requires that RX descriptors are posted in increments
 * of 4.  This means 'N' must be a multiple of four.  For the best
 * performance, the first new descriptor being posted should be (PCI)
 * cache line aligned.
 */

/* RX Completion Register.
 *
 * This 13-bit register is updated by GEM to indicate which RX descriptors
 * have already been used for receive frames.  All descriptors up to but
 * excluding the value in this register are ready to be processed.  GEM
 * updates this register value after the RX FIFO empties completely into
<