path: root/drivers/net/jme.h

/*
 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
 *
 * Copyright 2008 JMicron Technology Corporation
 * http://www.jmicron.com/
 *
 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#ifndef __JME_H_INCLUDED__
#define __JME_H_INCLUDED__

#define DRV_NAME	"jme"
#define DRV_VERSION	"1.0.4"
#define PFX		DRV_NAME ": "

#define PCI_DEVICE_ID_JMICRON_JMC250	0x0250
#define PCI_DEVICE_ID_JMICRON_JMC260	0x0260

/*
 * Message related definitions
 */
#define JME_DEF_MSG_ENABLE \
	(NETIF_MSG_PROBE | \
	NETIF_MSG_LINK | \
	NETIF_MSG_RX_ERR | \
	NETIF_MSG_TX_ERR | \
	NETIF_MSG_HW)

#define jeprintk(pdev, fmt, args...) \
	printk(KERN_ERR PFX fmt, ## args)

#ifdef TX_DEBUG
#define tx_dbg(priv, fmt, args...) \
	printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args)
#else
#define tx_dbg(priv, fmt, args...)
#endif

#define jme_msg(msglvl, type, priv, fmt, args...) \
	if (netif_msg_##type(priv)) \
		printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)

#define msg_probe(priv, fmt, args...) \
	jme_msg(KERN_INFO, probe, priv, fmt, ## args)

#define msg_link(priv, fmt, args...) \
	jme_msg(KERN_INFO, link, priv, fmt, ## args)

#define msg_intr(priv, fmt, args...) \
	jme_msg(KERN_INFO, intr, priv, fmt, ## args)

#define msg_rx_err(priv, fmt, args...) \
	jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)

#define msg_rx_status(priv, fmt, args...) \
	jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)

#define msg_tx_err(priv, fmt, args...) \
	jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)

#define msg_tx_done(priv, fmt, args...) \
	jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)

#define msg_tx_queued(priv, fmt, args...) \
	jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)

#define msg_hw(priv, fmt, args...) \
	jme_msg(KERN_ERR, hw, priv, fmt, ## args)

/*
 * Extra PCI Configuration space interface
 */
#define PCI_DCSR_MRRS		0x59
#define PCI_DCSR_MRRS_MASK	0x70

enum pci_dcsr_mrrs_vals {
	MRRS_128B	= 0x00,
	MRRS_256B	= 0x10,
	MRRS_512B	= 0x20,
	MRRS_1024B	= 0x30,
	MRRS_2048B	= 0x40,
	MRRS_4096B	= 0x50,
};

#define PCI_SPI			0xB0

enum pci_spi_bits {
	SPI_EN		= 0x10,
	SPI_MISO	= 0x08,
	SPI_MOSI	= 0x04,
	SPI_SCLK	= 0x02,
	SPI_CS		= 0x01,
};

struct jme_spi_op {
	void __user *uwbuf;
	void __user *urbuf;
	__u8	wn;	/* Number of write actions */
	__u8	rn;	/* Number of read actions */
	__u8	bitn;	/* Number of bits per action */
	__u8	spd;	/* The maxim acceptable speed of controller, in MHz.*/
	__u8	mode;	/* CPOL, CPHA, and Duplex mode of SPI */

	/* Internal use only */
	u8	*kwbuf;
	u8	*krbuf;
	u8	sr;
	u16	halfclk; /* Half of clock cycle calculated from spd, in ns */
};

enum jme_spi_op_bits {
	SPI_MODE_CPHA	= 0x01,
	SPI_MODE_CPOL	= 0x02,
	SPI_MODE_DUP	= 0x80,
};

#define HALF_US 500	/* 500 ns */
#define JMESPIIOCTL	SIOCDEVPRIVATE

/*
 * Dynamic(adaptive)/Static PCC values
 */
enum dynamic_pcc_values {
	PCC_OFF		= 0,
	PCC_P1		= 1,
	PCC_P2		= 2,
	PCC_P3		= 3,

	PCC_OFF_TO	= 0,
	PCC_P1_TO	= 1,
	PCC_P2_TO	= 64,
	PCC_P3_TO	= 128,

	PCC_OFF_CNT	= 0,
	PCC_P1_CNT	= 1,
	PCC_P2_CNT	= 16,
	PCC_P3_CNT	= 32,
};
struct dynpcc_info {
	unsigned long	last_bytes;
	unsigned long	last_pkts;
	unsigned long	intr_cnt;
	unsigned char	cur;
	unsigned char	attempt;
	unsigned char	cnt;
};
#define PCC_INTERVAL_US	100000
#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
#define PCC_P2_THRESHOLD 800
#define PCC_INTR_THRESHOLD 800
#define PCC_TX_TO 1000
#define PCC_TX_CNT 8

/*
 * TX/RX Descriptors
 *
 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
 */
#define RING_DESC_ALIGN		1