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|
/*
* drx3973d_map_firm.h
*
* Copyright (C) 2006-2007 Micronas
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 only, as published by the Free Software Foundation.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA
* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DRX3973D_MAP__H__
#define __DRX3973D_MAP__H__
/*
* Note: originally, this file contained 12000+ lines of data
* Probably a few lines for every firwmare assembler instruction. However,
* only a few defines were actually used. So, removed all uneeded lines.
* If ever needed, the other lines can be easily obtained via git history.
*/
#define HI_COMM_EXEC__A 0x400000
#define HI_COMM_MB__A 0x400002
#define HI_CT_REG_COMM_STATE__A 0x410001
#define HI_RA_RAM_SRV_RES__A 0x420031
#define HI_RA_RAM_SRV_CMD__A 0x420032
#define HI_RA_RAM_SRV_CMD_RESET 0x2
#define HI_RA_RAM_SRV_CMD_CONFIG 0x3
#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
#define HI_RA_RAM_SRV_RST_KEY__A 0x420033
#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
#define HI_RA_RAM_SRV_CFG_KEY__A 0x420033
#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034
#define HI_RA_RAM_SRV_CFG_BDL__A 0x420035
#define HI_RA_RAM_SRV_CFG_WUP__A 0x420036
#define HI_RA_RAM_SRV_CFG_ACT__A 0x420037
#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1
#define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4
#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0
#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4
#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8
#define HI_RA_RAM_USR_BEGIN__A 0x420040
#define HI_IF_RAM_TRP_BPT0__AX 0x430000
#define HI_IF_RAM_USR_BEGIN__A 0x430200
#define SC_COMM_EXEC__A 0x800000
#define SC_COMM_EXEC_CTL_STOP 0x0
#define SC_COMM_STATE__A 0x800001
#define SC_RA_RAM_PARAM0__A 0x820040
#define SC_RA_RAM_PARAM1__A 0x820041
#define SC_RA_RAM_CMD_ADDR__A 0x820042
#define SC_RA_RAM_CMD__A 0x820043
#define SC_RA_RAM_CMD_PROC_START 0x1
#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
#define SC_RA_RAM_CMD_GET_OP_PARAM 0x5
#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
#define SC_RA_RAM_LOCKTRACK_MIN 0x1
#define SC_RA_RAM_OP_PARAM_MODE_2K 0x0
#define SC_RA_RAM_OP_PARAM_MODE_8K 0x1
#define SC_RA_RAM_OP_PARAM_GUARD_32 0x0
#define SC_RA_RAM_OP_PARAM_GUARD_16 0x4
#define SC_RA_RAM_OP_PARAM_GUARD_8 0x8
#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC
#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
#define SC_RA_RAM_OP_PARAM_HIER_NO 0x0
#define SC_RA_RAM_OP_PARAM_HIER_A1 0x40
#define SC_RA_RAM_OP_PARAM_HIER_A2 0x80
#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
#define SC_RA_RAM_OP_AUTO_MODE__M 0x1
#define SC_RA_RAM_OP_AUTO_GUARD__M 0x2
#define SC_RA_RAM_OP_AUTO_CONST__M 0x4
#define SC_RA_RAM_OP_AUTO_HIER__M 0x8
#define SC_RA_RAM_OP_AUTO_RATE__M 0x10
#define SC_RA_RAM_LOCK__A 0x82004B
#define SC_RA_RAM_LOCK_DEMOD__M 0x1
#define SC_RA_RAM_LOCK_FEC__M 0x2
#define SC_RA_RAM_LOCK_MPEG__M 0x4
#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C
#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1
#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D
#define SC_RA_RAM_CONFIG__A 0x820050
#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4
#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10
#define SC_RA_RAM_CONFIG_SLAVE__M 0x20
#define SC_RA_RAM_IF_SAVE__AX 0x82008E
#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9
#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2
#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4
#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3
#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100
#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4
#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8
#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5
#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8
#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6
#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200
#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7
#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9
#define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8
#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4
#define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9
#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100
#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA
#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB
#define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB
#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1
#define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC
#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40
#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD
#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8
#define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9
#define SC_RA_RAM_BAND__A 0x8200EC
#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4
#define SC_RA_RAM_LC_ABS_2K__PRE 0x1F
#define SC_RA_RAM_LC_ABS_8K__A 0x8200F5
#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6
#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB
#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A
#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197
#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5
#define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE
#define SC_RA_RAM_PROC_LOCKTRACK 0x0
#define FE_COMM_EXEC__A 0xC00000
#define FE_AD_REG_COMM_EXEC__A 0xC10000
#define FE_AD_REG_FDB_IN__A 0xC10012
#define FE_AD_REG_PD__A 0xC10013
#define FE_AD_REG_INVEXT__A 0xC10014
#define FE_AD_REG_CLKNEG__A 0xC10015
#define FE_AG_REG_COMM_EXEC__A 0xC20000
#define FE_AG_REG_AG_MODE_LOP__A 0xC20010
#define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10
#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0
#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10
#define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20
#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0
#define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000
#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0
#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000
#define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000
#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0
#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000
#define FE_AG_REG_AG_MODE_HIP__A 0xC20011
#define FE_AG_REG_AG_PGA_MODE__A 0xC20012
#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0
#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1
#define FE_AG_REG_AG_AGC_SIO__A 0xC20013
#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2
#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0
#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2
#define FE_AG_REG_AG_PWD__A 0xC20015
#define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2
#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0
#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2
#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016
#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017
#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A
#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B
#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020
#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024
#define FE_AG_REG_EGC_SET_LVL__A 0xC20025
#define FE_AG_REG_EGC_SET_LVL__M 0x1FF
#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026
#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027
#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028
#define FE_AG_REG_EGC_FLA_INC__A 0xC20029
#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A
#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B
#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C
#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D
#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E
#define FE_AG_REG_PM1_AGC_WRI__A 0xC20030
#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF
#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031
#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032
#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033
#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034
#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035
#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF
#define FE_AG_REG_PM2_AGC_WRI__A 0xC20036
#define FE_AG_REG_IND_WIN__A 0xC2003C
#define FE_AG_REG_IND_THD_LOL__A 0xC2003D
#define FE_AG_REG_IND_THD_HIL__A 0xC2003E
#define FE_AG_REG_IND_DEL__A 0xC2003F
#define FE_AG_REG_IND_PD1_WRI__A 0xC20040
#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041
#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042
#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043
#define FE_AG_REG_PDC_RUR_CNT__A 0xC20044
#define FE_AG_REG_PDC_SET_LVL__A 0xC20045
#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046
#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047
#define FE_AG_REG_PDC_FLA_STP__A 0xC20048
#define FE_AG_REG_PDC_SLO_STP__A 0xC20049
#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A
#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B
#define FE_AG_REG_PDC_MAX__A 0xC2004C
#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D
#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E
#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F
#define FE_AG_REG_TGC_RUR_CNT__A 0xC20050
#define FE_AG_REG_TGC_SET_LVL__A 0xC20051
#define FE_AG_REG_TGC_SET_LVL__M 0x3F
#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052
#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053
#
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