1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
|
/*
* Copyright 2010 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_bios.h"
#include "nouveau_pm.h"
struct nv50_pm_state {
struct nouveau_pm_level *perflvl;
struct pll_lims pll;
enum pll_types type;
int N, M, P;
};
int
nv50_pm_clock_get(struct drm_device *dev, u32 id)
{
struct pll_lims pll;
int P, N, M, ret;
u32 reg0, reg1;
ret = get_pll_limits(dev, id, &pll);
if (ret)
return ret;
reg0 = nv_rd32(dev, pll.reg + 0);
reg1 = nv_rd32(dev, pll.reg + 4);
if ((reg0 & 0x80000000) == 0) {
if (id == PLL_SHADER) {
NV_DEBUG(dev, "Shader PLL is disabled. "
"Shader clock is twice the core\n");
ret = nv50_pm_clock_get(dev, PLL_CORE);
if (ret > 0)
return ret << 1;
} else if (id == PLL_MEMORY) {
NV_DEBUG(dev, "Memory PLL is disabled. "
"Memory clock is equal to the ref_clk\n");
return pll.refclk;
}
}
P = (reg0 & 0x00070000) >> 16;
N = (reg1 & 0x0000ff00) >> 8;
M = (reg1 & 0x000000ff);
return ((pll.refclk * N / M) >> P);
}
void *
nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
u32 id, int khz)
{
struct nv50_pm_state *state;
int dummy, ret;
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return ERR_PTR(-ENOMEM);
state->type = id;
state->perflvl = perflvl;
ret = get_pll_limits(dev, id, &state->pll);
if (ret < 0) {
kfree(state);
return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
}
ret = nv50_calc_pll(dev, &state->pll, khz, &state->N, &state->M,
&dummy, &dummy, &state->P);
if (ret < 0) {
kfree(state);
return ERR_PTR(ret);
}
return state;
}
void
nv50_pm_clock_set(struct drm_device *dev, void *pre_state)
{
struct nv50_pm_state *state = pre_state;
struct nouveau_pm_level *perflvl = state->perflvl;
u32 reg = state->pll.reg, tmp;
struct bit_entry BIT_M;
u16 script;
int N = state->N;
int M = state->M;
int P = state->P;
if (state->type == PLL_MEMORY && perflvl->memscript &&
bit_table(dev, 'M', &BIT_M) == 0 &&
BIT_M.version == 1 && BIT_M.length >= 0x0b) {
script = ROM16(BIT_M.data[0x05]);
if (script)
nouveau_bios_run_init_table(dev, script, NULL);
script = ROM16(BIT_M.data[0x07]);
if (script)
nouveau_bios_run_init_table(dev, script, NULL);
script = ROM16(BIT_M.data[0x09]);
if (script)
nouveau_bios_run_init_table(dev, script, NULL);
nouveau_bios_run_init_table(dev, perflvl->memscript, NULL);
}
if (state->type == PLL_MEMORY) {
nv_wr32(dev, 0x100210, 0);
nv_wr32(dev, 0x1002dc, 1);
}
tmp = nv_rd32(dev, reg + 0) & 0xfff8ffff;
tmp |= 0x80000000 | (P << 16);
nv_wr32(dev, reg + 0, tmp);
nv_wr32(dev, reg + 4, (N << 8) | M);
if (state->type == PLL_MEMORY) {
nv_wr32(dev, 0x1002dc, 0);
nv_wr32(dev, 0x100210, 0x80000000);
}
kfree(state);
}
|
