1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
|
/*
* GPIO interface for Intel Sodaville SoCs.
*
* Copyright (c) 2010, 2011 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License 2 as published
* by the Free Software Foundation.
*
*/
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/of_irq.h>
#include <linux/basic_mmio_gpio.h>
#define DRV_NAME "sdv_gpio"
#define SDV_NUM_PUB_GPIOS 12
#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
#define GPIO_BAR 0
#define GPOUTR 0x00
#define GPOER 0x04
#define GPINR 0x08
#define GPSTR 0x0c
#define GPIT1R0 0x10
#define GPIO_INT 0x14
#define GPIT1R1 0x18
#define GPMUXCTL 0x1c
struct sdv_gpio_chip_data {
int irq_base;
void __iomem *gpio_pub_base;
struct irq_domain id;
struct irq_chip_generic *gc;
struct bgpio_chip bgpio;
};
static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct sdv_gpio_chip_data *sd = gc->private;
void __iomem *type_reg;
u32 irq_offs = d->irq - sd->irq_base;
u32 reg;
if (irq_offs < 8)
type_reg = sd->gpio_pub_base + GPIT1R0;
else
type_reg = sd->gpio_pub_base + GPIT1R1;
reg = readl(type_reg);
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
reg &= ~BIT(4 * (irq_offs % 8));
break;
case IRQ_TYPE_LEVEL_LOW:
reg |= BIT(4 * (irq_offs % 8));
break;
default:
return -EINVAL;
}
writel(reg, type_reg);
return 0;
}
static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
{
struct sdv_gpio_chip_data *sd = data;
u32 irq_stat = readl(sd->gpio_pub_base + GPSTR);
irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
if (!irq_stat)
return IRQ_NONE;
while (irq_stat) {
u32 irq_bit = __fls(irq_stat);
irq_stat &= ~BIT(irq_bit);
generic_handle_irq(sd->irq_base + irq_bit);
}
return IRQ_HANDLED;
}
static int sdv_xlate(struct irq_domain *h, struct device_node *node,
const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
u32 *out_type)
{
u32 line, type;
if (node != h->of_node)
return -EINVAL;
if (intsize < 2)
return -EINVAL;
line = *intspec;
*out_hwirq = line;
intspec++;
type = *intspec;
switch (type) {
case IRQ_TYPE_LEVEL_LOW:
case IRQ_TYPE_LEVEL_HIGH:
*out_type = type;
break;
default:
return -EINVAL;
}
return 0;
}
static struct irq_domain_ops irq_domain_sdv_ops = {
.dt_translate = sdv_xlate,
};
static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
struct pci_dev *pdev)
{
struct irq_chip_type *ct;
int ret;
sd->irq_base = irq_alloc_descs(-1, 0, SDV_NUM_PUB_GPIOS, -1);
if (sd->irq_base < 0)
return sd->irq_base;
/* mask + ACK all interrupt sources */
writel(0, sd->gpio_pub_base + GPIO_INT);
writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
"sdv_gpio", sd);
if (ret)
goto out_free_desc;
sd->id.irq_base = sd->irq_base;
sd->id.of_node = of_node_get(pdev->dev.of_node);
sd->id.ops = &irq_domain_sdv_ops;
/*
* This gpio irq controller latches level irqs. Testing shows that if
* we unmask & ACK the IRQ before the source of the interrupt is gone
* then the interrupt is active again.
*/
sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
sd->gpio_pub_base, handle_fasteoi_irq);
if (!sd->gc) {
ret = -ENOMEM;
goto out_free_irq;
}
sd->gc->private = sd;
ct = sd->gc->chip_types;
ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
ct->regs.eoi = GPSTR;
ct->regs.mask = GPIO_INT;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_eoi = irq_gc_eoi;
ct->chip.irq_set_type = sdv_gpio_pub_set_type;
irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
IRQ_LEVEL | IRQ_NOPROBE);
irq_domain_add(&sd->id);
return 0;
out_free_irq:
free_irq(pdev->irq, sd);
out_free_desc:
irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
return ret;
}
static int __devinit sdv_gpio_probe(struct pci_dev *pdev,
const struct pci_device_id *pci_id)
{
struct sdv_gpio_chip_data *sd;
unsigned long addr;
const void *prop;
int len;
int ret;
u32 mux_val;
sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL);
if (!sd)
return -ENOMEM;
ret = pci_enable_device(pdev);
if (ret) {
dev_err(&pdev->dev, "can't enable device.\n");
goto done;
}
ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
if (ret) {
dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
goto disable_pci;
}
addr = pci_resource_start(pdev, GPIO_BAR);
if (!addr)
goto release_reg;
sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR));
prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len);
if (prop && len == 4) {
mux_val = of_read_number(prop, 1);
writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
}
ret = bgpio_init(&sd->bgpio, &pdev->dev, 4,
sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
NULL, sd->gpio_pub_base + GPOER, NULL, false);
if (ret)
goto unmap;
sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS;
ret = gpiochip_add(&sd->bgpio.gc);
if (ret < 0) {
dev_err(&pdev->dev, "gpiochip_add() failed.\n");
goto unmap;
}
ret = sdv_register_irqsupport(sd, pdev);
if (ret)
goto unmap;
pci_set_drvdata(pdev, sd);
dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
return 0;
unmap:
iounmap(sd->gpio_pub_base);
release_reg:
pci_release_region(pdev, GPIO_BAR);
disable_pci:
pci_disable_device(pdev);
done:
kfree(sd);
return ret;
}
static void sdv_gpio_remove(struct pci_dev *pdev)
{
struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
irq_domain_del(&sd->id);
free_irq(pdev->irq, sd);
irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
if (gpiochip_remove(&sd->bgpio.gc))
dev_err(&pdev->dev, "gpiochip_remove() failed.\n");
pci_release_region(pdev, GPIO_BAR);
iounmap(sd->gpio_pub_base);
pci_disable_device(pdev);
kfree(sd);
}
static struct pci_device_id sdv_gpio_pci_ids[] __devinitdata = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
{ 0, },
};
static struct pci_driver sdv_gpio_driver = {
.name = DRV_NAME,
.id_table = sdv_gpio_pci_ids,
.probe = sdv_gpio_probe,
.remove = sdv_gpio_remove,
};
static int __init sdv_gpio_init(void)
{
return pci_register_driver(&sdv_gpio_driver);
}
module_init(sdv_gpio_init);
static void __exit sdv_gpio_exit(void)
{
pci_unregister_driver(&sdv_gpio_driver);
}
module_exit(sdv_gpio_exit);
MODULE_AUTHOR("Hans J. Koch <hjk@linutronix.de>");
MODULE_DESCRIPTION("GPIO interface for Intel Sodaville SoCs");
MODULE_LICENSE("GPL v2");
|
