/* * DMA driver for Nvidia's Tegra20 APB DMA controller. * * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */#include<linux/bitops.h>#include<linux/clk.h>#include<linux/delay.h>#include<linux/dmaengine.h>#include<linux/dma-mapping.h>#include<linux/init.h>#include<linux/interrupt.h>#include<linux/io.h>#include<linux/mm.h>#include<linux/module.h>#include<linux/of.h>#include<linux/of_device.h>#include<linux/platform_device.h>#include<linux/pm_runtime.h>#include<linux/slab.h>#include<mach/clk.h>#include"dmaengine.h"#define TEGRA_APBDMA_GENERAL 0x0#define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)#define TEGRA_APBDMA_CONTROL 0x010#define TEGRA_APBDMA_IRQ_MASK 0x01c#define TEGRA_APBDMA_IRQ_MASK_SET 0x020/* CSR register */#define TEGRA_APBDMA_CHAN_CSR 0x00#define TEGRA_APBDMA_CSR_ENB BIT(31)#define TEGRA_APBDMA_CSR_IE_EOC BIT(30)#define TEGRA_APBDMA_CSR_HOLD BIT(29)#define TEGRA_APBDMA_CSR_DIR BIT(28)#define TEGRA_APBDMA_CSR_ONCE BIT(27)#define TEGRA_APBDMA_CSR_FLOW BIT(21)#define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16#define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC/* STATUS register */#define TEGRA_APBDMA_CHAN_STATUS 0x004#define TEGRA_APBDMA_STATUS_BUSY BIT(31)#define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)#define TEGRA_APBDMA_STATUS_HALT BIT(29)#define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)#define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2#define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC#define TEGRA_APBDMA_CHAN_CSRE 0x00C#define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)/* AHB memory address */#define TEGRA_APBDMA_CHAN_AHBPTR 0x010/* AHB sequence register */#define TEGRA_APBDMA_CHAN_AHBSEQ 0x14#define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)#define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)#define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)#define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)#define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)#define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)#define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)#define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16#de
