/* * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */#include<linux/io.h>#include<linux/delay.h>#include<linux/clk.h>#include<linux/clk-provider.h>#include<linux/clkdev.h>#include<linux/of.h>#include<linux/of_address.h>#include<linux/clk/tegra.h>#include<linux/tegra-powergate.h>#include<dt-bindings/clock/tegra30-car.h>#include"clk.h"#include"clk-id.h"#define OSC_CTRL 0x50#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)#define OSC_FREQ_DET 0x58#define OSC_FREQ_DET_TRIG BIT(31)#define OSC_FREQ_DET_STATUS 0x5c#define OSC_FREQ_DET_BUSY BIT(31)#define OSC_FREQ_DET_CNT_MASK 0xffff#define CCLKG_BURST_POLICY 0x368#define SUPER_CCLKG_DIVIDER 0x36c#define CCLKLP_BURST_POLICY 0x370#define SUPER_CCLKLP_DIVIDER 0x374#define SCLK_BURST_POLICY 0x028#define SUPER_SCLK_DIVIDER 0x02c#define SYSTEM_CLK_RATE 0x030#define TEGRA30_CLK_PERIPH_BANKS 5#define PLLC_BASE 0x80#define PLLC_MISC 0x8c#define PLLM_BASE 0x90#define PLLM_MISC 0x9c#define PLLP_BASE 0xa0#define PLLP_MISC 0xac#define PLLX_BASE 0xe0#define PLLX_MISC 0xe4#define PLLD_BASE 0xd0#define PLLD_MISC 0xdc#define PLLD2_BASE 0x4b8#define PLLD2_MISC 0x4bc#define PLLE_BASE 0xe8#define PLLE_MISC 0xec#define PLLA_BASE 0xb0#define PLLA_MISC 0xbc#define PLLU_BASE 0xc0#define PLLU_MISC 0xcc#define PLL_MISC_LOCK_ENABLE 18#define PLLDU_MISC_LOCK_ENABLE 22#define PLLE_MISC_LOCK_ENABLE 9#define PLL_BASE_LOCK BIT(27)#define PLLE_MISC_LOCK BIT(11)#define PLLE_AUX 0x48c#define PLLC_OUT 0x84#define PLLM_OUT 0x94#define PLLP_OUTA 0xa4#define PLLP_OUTB 0xa8#define PLLA_OUT 0xb4#define AUDIO_SYNC_CLK_I2S0 0x4a0#define AUDIO_SYNC_CLK_I2S1 0x4a4#define AUDIO_SYNC_CLK_I2S2 0x4a8#define AUDIO_SYNC_CLK_I2S3 0x4ac#define AUDIO_SYNC_CLK_I2S4 0x4b0#define AUDIO_SYNC_CLK_SPDIF 0x4b4#define CLK_SOURCE_SPDIF_OUT 0x108#define CLK_SOURCE_PWM 0x110#define CLK_SOURCE_D_AUDIO 0x3d0#define CLK_SOURCE_DAM0 0x3d8#define CLK_SOURCE_DAM1 0x3dc#define CLK_SOURCE_DAM2 0x3e0#define CLK_SOURCE_3D2 0x3b0#define CLK_SOURCE_2D 0x15c#define CLK_SOURCE_HDMI 0x18c#define CLK_SOURCE_DSIB 0xd0#define CLK_SOURCE_SE 0x42c
