path: root/drivers/atm/idt77252.h

/******************************************************************* 
 * ident "$Id: idt77252.h,v 1.2 2001/11/11 08:13:54 ecd Exp $"
 *
 * $Author: ecd $
 * $Date: 2001/11/11 08:13:54 $
 *
 * Copyright (c) 2000 ATecoM GmbH 
 *
 * The author may be reached at ecd@atecom.com.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
 * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *******************************************************************/

#ifndef _IDT77252_H
#define _IDT77252_H 1


#include <linux/ptrace.h>
#include <linux/skbuff.h>
#include <linux/workqueue.h>


/*****************************************************************************/
/*                                                                           */
/* Makros                                                                    */
/*                                                                           */
/*****************************************************************************/
#define VPCI2VC(card, vpi, vci) \
        (((vpi) << card->vcibits) | ((vci) & card->vcimask))

/*****************************************************************************/
/*                                                                           */
/*   DEBUGGING definitions                                                   */
/*                                                                           */
/*****************************************************************************/

#define DBG_RAW_CELL	0x00000400
#define DBG_TINY	0x00000200
#define DBG_GENERAL     0x00000100
#define DBG_XGENERAL    0x00000080
#define DBG_INIT        0x00000040
#define DBG_DEINIT      0x00000020
#define DBG_INTERRUPT   0x00000010
#define DBG_OPEN_CONN   0x00000008
#define DBG_CLOSE_CONN  0x00000004
#define DBG_RX_DATA     0x00000002
#define DBG_TX_DATA     0x00000001

#ifdef CONFIG_ATM_IDT77252_DEBUG

#define CPRINTK(args...)   do { if (debug & DBG_CLOSE_CONN) printk(args); } while(0)
#define OPRINTK(args...)   do { if (debug & DBG_OPEN_CONN)  printk(args); } while(0)
#define IPRINTK(args...)   do { if (debug & DBG_INIT)       printk(args); } while(0)
#define INTPRINTK(args...) do { if (debug & DBG_INTERRUPT)  printk(args); } while(0)
#define DIPRINTK(args...)  do { if (debug & DBG_DEINIT)     printk(args); } while(0)
#define TXPRINTK(args...)  do { if (debug & DBG_TX_DATA)    printk(args); } while(0)
#define RXPRINTK(args...)  do { if (debug & DBG_RX_DATA)    printk(args); } while(0)
#define XPRINTK(args...)   do { if (debug & DBG_XGENERAL)   printk(args); } while(0)
#define DPRINTK(args...)   do { if (debug & DBG_GENERAL)    printk(args); } while(0)
#define NPRINTK(args...)   do { if (debug & DBG_TINY)	    printk(args); } while(0)
#define RPRINTK(args...)   do { if (debug & DBG_RAW_CELL)   printk(args); } while(0)

#else

#define CPRINTK(args...)	do { } while(0)
#define OPRINTK(args...)	do { } while(0)
#define IPRINTK(args...)	do { } while(0)
#define INTPRINTK(args...)	do { } while(0)
#define DIPRINTK(args...)	do { } while(0)
#define TXPRINTK(args...)	do { } while(0)
#define RXPRINTK(args...)	do { } while(0)
#define XPRINTK(args...)	do { } while(0)
#define DPRINTK(args...)	do { } while(0)
#define NPRINTK(args...)	do { } while(0)
#define RPRINTK(args...)	do { } while(0)

#endif

#define SCHED_UBR0		0
#define SCHED_UBR		1
#define SCHED_VBR		2
#define SCHED_ABR		3
#define SCHED_CBR		4

#define SCQFULL_TIMEOUT		HZ

/*****************************************************************************/
/*                                                                           */
/*   Free Buffer Queue Layout                                                */
/*                                                                           */
/*****************************************************************************/
#define SAR_FB_SIZE_0		(2048 - 256)
#define SAR_FB_SIZE_1		(4096 - 256)
#define SAR_FB_SIZE_2		(8192 - 256)
#define SAR_FB_SIZE_3		(16384 - 256)

#define SAR_FBQ0_LOW		4
#define SAR_FBQ0_HIGH		8
#define SAR_FBQ1_LOW		2
#define SAR_FBQ1_HIGH		4
#define SAR_FBQ2_LOW		1
#define SAR_FBQ2_HIGH		2
#define SAR_FBQ3_LOW		1
#define SAR_FBQ3_HIGH		2

#if 0
#define SAR_TST_RESERVED	44	/* Num TST reserved for UBR/ABR/VBR */
#else
#define SAR_TST_RESERVED	0	/* Num TST reserved for UBR/ABR/VBR */
#endif

#define TCT_CBR			0x00000000
#define TCT_UBR			0x00000000
#define TCT_VBR			0x40000000
#define TCT_ABR			0x80000000
#define TCT_TYPE		0xc0000000

#define TCT_RR			0x20000000
#define TCT_LMCR		0x08000000
#define TCT_SCD_MASK		0x0007ffff

#define TCT_TSIF		0x00004000
#define TCT_HALT		0x80000000
#define TCT_IDLE		0x40000000
#define TCT_FLAG_UBR		0x80000000

/*****************************************************************************/
/*                                                                           */
/*   Structure describing an IDT77252                                        */
/*                                                                           */
/*****************************************************************************/

struct scqe
{
	u32		word_1;
	u32		word_2;
	u32		word_3;
	u32		word_4;
};

#define SCQ_ENTRIES	64
#define SCQ_SIZE	(SCQ_ENTRIES * sizeof(struct scqe))
#define SCQ_MASK	(SCQ_SIZE - 1)

struct scq_info
{
	struct scqe		*base;
	struct scqe		*next;
	struct scqe		*last;
	dma_addr_t		paddr;
	spinlock_t		lock;
	atomic_t		used;
	unsigned long		trans_start;
        unsigned long		scd;
	spinlock_t		skblock;
	struct sk_buff_head	transmit;
	struct sk_buff_head	pending;
};

struct rx_pool {
	struct sk_buff		*first;
	struct sk_buff		**last;
	unsigned int		len;
	unsigned int		count;
};

struct aal1 {
	unsigned int		total;
	unsigned int		count;
	struct sk_buff		*data;
	unsigned char		sequence;
};

struct rate_estimator {
	struct timer_list	timer;
	unsigned int		interval;
	unsigned int		ewma_log;
	u64			cells;
	u64			last_cells;
	long			avcps;
	u32			cps;
	u32			maxcps;
};

struct vc_map {
	unsigned int		index;
	unsigned long		flags;
#define VCF_TX		0
#define VCF_RX		1
#define VCF_IDLE	2
#define VCF_RSV		3
	unsigned int		class;
	u8			init_er;
	u8			lacr;
	u8			max_er;
	unsigned int		ntste;
	spinlock_t		lock;
	struct atm_vcc		*tx_vcc;
	struct atm_vcc		*rx_vcc;
	struct idt77252_dev	*card;
	struct scq_info		*scq;		/* To keep track of the SCQ */
	struct rate_estimator	*estimator;
	int			scd_index;
	union {
		struct rx_pool	rx_pool;
		struct aal1	aal1;
	} rcv;
};

/*****************************************************************************/
/*                                                                           */
/*   RCTE - Receive Connection Table Entry                                   */
/*                                                                           */
/*****************************************************************************/

struct rct_entry
{
	u32		word_1;
	u32		buffer_handle;
	u32		dma_address;
	u32		aal5_crc32;
};

/*****************************************************************************/
/*                                                                           */
/*   RSQ - Receive Status Queue                                              */
/*                                                                           */
/*****************************************************************************/

#define SAR_RSQE_VALID      0x80000000
#define SAR_RSQE_IDLE       0x40000000
#define SAR_RSQE_BUF_MASK   0x00030000
#define SAR_RSQE_BUF_ASGN   0x00008000
#define SAR_RSQE_NZGFC      0x00004000
#define SAR_RSQE_EPDU       0x00002000
#define SAR_RSQE_BUF_CONT   0x00001000
#define SAR_RSQE_EFCIE      0x00000800
#define SAR_RSQE_CLP        0x00000400
#define SAR_RSQE_CRC        0x00000200
#define SAR_RSQE_CELLCNT    0x000001FF


#define RSQSIZE            8192
#define RSQ_NUM_ENTRIES    (RSQSIZE / 16)
#define RSQ_ALIGNMENT      8192

struct rsq_entry {
	u32			word_1;
	u32			word_2;
	u32			word_3;
	u32			word_4;
};

struct rsq_info {
	struct rsq_entry	*base;
	struct rsq_entry	*next;
	struct rsq_entry	*last;
	dma_addr_t		paddr;
};


/*****************************************************************************/
/*                                                                           */
/*   TSQ - Transmit Status Queue                                             */
/*                                                                           */
/*****************************************************************************/

#define SAR_TSQE_INVALID         0x80000000
#define SAR_TSQE_TIMESTAMP       0x00FFFFFF
#define SAR_TSQE_TYPE		 0x60000000
#define SAR_TSQE_TYPE_TIMER      0x00000000
#define SAR_TSQE_TYPE_TSR        0x20000000
#define SAR_TSQE_TYPE_IDLE       0x40000000
#define SAR_TSQE_TYPE_TBD_COMP   0x60000000

#define SAR_TSQE_TAG(stat)	(((stat) >> 24) & 0x1f)

#define TSQSIZE            8192
#define TSQ_NUM_ENTRIES    1024
#define TSQ_ALIGNMENT      8192

struct tsq_entry
{
	u32			word_1;
	u32			word_2;
};

struct tsq_info
{
	struct tsq_entry	*base;
	struct tsq_entry	*next;
	struct tsq_entry	*last;
	dma_addr_t		paddr;
};

struct tst_info
{
	struct vc_map		*vc;
	u32			tste;
};

#define TSTE_MASK		0x601fffff

#define TSTE_OPC_MASK		0x60000000
#define TSTE_OPC_NULL		0x00000000
#define TSTE_OPC_CBR		0x20000000
#define TSTE_OPC_VAR		0x40000000
#define TSTE_OPC_JMP		0x60000000

#define TSTE_PUSH_IDLE		0x01000000
#define TSTE_PUSH_ACTIVE	0x02000000

#define TST_SWITCH_DONE		0
#define TST_SWITCH_PENDING	1
#define TST_SWITCH_WAIT		2

#define FBQ_SHIFT		9
#define FBQ_SIZE		(1 << FBQ_SHIFT)
#define FBQ_MASK		(FBQ_SIZE - 1)

struct sb_pool
{
	unsigned int		index;
	struct sk_buff		*skb[FBQ_SIZE];
};

#define POOL_HANDLE(queue, index)	(((queue + 1) << 16) | (index))
#define POOL_QUEUE(handle)		(((handle) >> 16) - 1)
#define POOL_INDEX(handle)		((handle) & 0xffff)

struct idt77252_dev
{
        struct tsq_info		tsq;		/* Transmit Status Queue */
        struct rsq_info		rsq;		/* Receive Status Queue */

	struct pci_dev		*pcidev;	/* PCI handle (desriptor) */
	struct atm_dev		*atmdev;	/* ATM device desriptor */

	void __iomem